Commit Graph

26556 Commits

Author SHA1 Message Date
Elyes HAOUAS d37a5bc29e mb/pcengines: Remove unneeded includes and dead code
Fix coding style.

Change-Id: Id13c0ee284293c0c06d46c75c850bc7e81cfc1f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-06-17 15:37:46 +00:00
Arthur Heymans df946b8696 nb/intel/x4x: Issue a hard reset with empty MRC cache on warm reset
The dram controller cannot fully initialize the dram on warm
reset (receive enable calibration consistently fails) therefore
requiring cached timings.

This option is mostly useful when rebooting after having flashed a new
rom which overwrites the mrc cache region.

Change-Id: I405c0eca076fe081641ede9a670f734c98cbf8fc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-06-17 14:17:31 +00:00
Kyösti Mälkki 76f7b79fb8 drivers/spi: Add Winbond W25Q80
This is a small 8 megabit (1 MiB) part.

Change-Id: I9890457d0d14beb17d0a428c2701e620ae8c2512
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-16 18:22:27 +00:00
Martin Roth 3711479c27 mainboard/google/Kahlee: All variants identify as Grunt in SMBIOS
All Grunt variants should identify as grunt in SMBIOS so that
they're recognized correctly as a unibuild Grunt variant.

BUG=b:110244268
TEST=Careena identifies as grunt

Change-Id: Iaf254149fbec9551d9220018d6d6a0a1be741538
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/27117
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-15 14:42:25 +00:00
Patrick Rudolph 0d42a2c421 Documentation: Add SandyBridge NRI feature matrix
Change-Id: I69b014430802de132c8d9b6c8409bc762b995468
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27093
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-15 09:15:20 +00:00
Hannah Williams cf45830982 soc/intel/{glk,apl} and mainboards: Configure LPC_CLKRUN# pin as GPIO for S0ix
This pin does not have a native function for eSPI. Nonetheless if we use
eSPI, it should be configured as a GPIO and kept unconnected to allow
S0ix entry.

Also removed initialization of LPC pins in mainboard code as they are
already initialized in chipset code. The settings fpr LPC pins in 
chipset code were updated to those that were previously in mainboard 
code and have been validated on LPC flavor of Geminilake RVP.

BUG=b:79251613
BRANCH=none
TEST=From kernel prompt in bip, type powerd_dbus_suspend.
Check on EC console that SOC enters S0ix.

Change-Id: Ie0c1013fee638a3b7a91469736efc0c25a1597fa
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/23742
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-15 09:14:35 +00:00
Patrick Rudolph 7ee05eddf1 util/cbfstool: Support FIT payloads
In order to support booting a GNU/Linux payload on non x86, the FIT format
should be used, as it is the defacto standard on ARM.
Due to greater complexity of FIT it is not converted to simple ELF format.

Add support for autodecting FIT payloads and add them as new CBFS_TYPE 'fit'.
The payload is included as is, with no special header.
The code can determine the type at runtime using the CBFS_TYPE field.
Support for parsing FIT payloads in coreboot is added in a follow on
commit.
Compression of FIT payloads is not supported, as the FIT sections might be
compressed itself.

Starting at this point a CBFS payload/ can be either of type FIT or SELF.

Tested on Cavium SoC.

Change-Id: Ic5fc30cd5419eb76c4eb50cca3449caea60270de
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-15 09:13:24 +00:00
John Su 31ff06a2da mb/google/poppy/variants/nami: Update DPTF table from version 1.5
Update dptf.asl and TCC parameters from tuning of the thermal team.

BUG=b:72974136
TEST=Match the result from DPTF UI

Change-Id: Ic0ffc169ad3939cacb46824ed23999c61a23d2c4
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27086
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-15 08:14:27 +00:00
Kevin Chiu 56dfc93751 mainboard/google/kahlee: Enable keyboard backlight for careena specific SKU
Enable keyboard backlight by Careena SKUID
Set to 10% as the same as google/snappy project

BUG=b:110065836
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I7d302c4f50528b0e6b7ef4d990f342a69cff34f5
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/27021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-15 08:14:11 +00:00
Arthur Heymans faa5f9869d cpu/intel/haswell: Use the common intel romstage_main function
Tested on Google peppy (Acer C720).

Change-Id: I6453c40bf4ebe4695684c1bd3a403d6def82814f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-14 10:01:35 +00:00
Elyes HAOUAS 5e2ac2c079 nb/intel/fsp_rangeley: Use MSR_PLATFORM_INFO instead of 0xce
Change-Id: Ifb8aa43b6545482bc7fc136a90c4bbaa18d46089
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/22957
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14 10:00:03 +00:00
Arthur Heymans e73a85c5a5 driver/spi/macronix.c: Add MX25L8005
Change-Id: I595198d66193c63f6c80c39371fbec10065d2165
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14 09:49:56 +00:00
Elyes HAOUAS 17fd13a4a7 arch/arm/armv7: Fix coding style
Change-Id: Ib5d574347373009c8021597f555e6e86c2c0c41f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14 09:49:39 +00:00
Elyes HAOUAS 27929bd0b0 cpu/amd: Remove duplicated includes
Change-Id: I3544ce4a573b6996d64b140d8acdaeb3de430896
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-14 09:44:49 +00:00
Arthur Heymans 2abde07b9d mb/lenovo/x200: Enable libgfxinit
Change-Id: I6919845965d90fe8a20a07748ae4804fed0d0cef
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27013
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14 09:41:28 +00:00
Arthur Heymans e8093054d3 nb/intel/x4x: Deprecate native graphic init
Libgfxinit provides a better alternative to the native C init. While
libgfxinit mandates an ada compiler, we want to encourage use of it
since it is in much better shape and is actually maintained.

This way libgfxinit also gets build-tested by Jenkins.

Change-Id: I4843f52307b87cff6fa6f4d0c74b87428fefa8ac
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14 09:40:55 +00:00
Arthur Heymans 1ce4bf9717 mb/*/*: Enable libgfxinit on x4x boards
TESTED Intel DG41WV with VGA, Intel DG43GT with VGA and HDMI1 and
HDMI2.

Change-Id: I774b79cc0ef9dc72ccf48901ab94376b27ed9c7a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14 09:40:20 +00:00
Arthur Heymans 7345a17a43 nb/intel/x4x: Fix a few things in set_enhanced_mode
Some things were coding errors, other things need to be fsb specific.

Most things here don't seem to matter all that much but better to get
it right.

Change-Id: I1afa637a16a083c3a945ba3e2a71292b005736fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14 09:37:50 +00:00
Arthur Heymans 5a9dbde59c nb/intel/x4x: Work around a quirk
It looks like this hardware has a bug where the display controller
does not work properly when dram is clocked 533MHz and the channels
are configured in non-stacked mode.

The workaround is to select stacked mode in this configuration.

Change-Id: I6f37ce15a4e98a4cdbd6d893f22846a65c8be021
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-06-14 09:36:04 +00:00
Arthur Heymans 0602ce67a6 nb/intel/x4x: Add the option for stacked channel map settings
There seems to be a hardware bug where the combination of non-stacked
channel settings, both channels populated and 533MHz dram speed cause
the display to be unusable.

The code to actually select stacked mode based on hardware
configuration will be add in a followup patch.

This patch does the following:
* Add option to the sysinfo struct for stacked mode
* Fix programming channel 1 DRB which needs special care for the last
  populated rank in stacked mode

TESTED on Intel dg41wv (with stacked mode hardcoded and dram at 533MHz)

Change-Id: I95965bfea129b37f64163159fefa1c8f16331b62
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14 09:35:30 +00:00
Elyes HAOUAS b0f1988f89 src: Get rid of unneeded whitespace
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14 09:32:34 +00:00
Elyes HAOUAS 68c851bcd7 src: Get rid of device_t
Use of device_t is deprecated.

Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14 09:30:24 +00:00
Elyes HAOUAS c8a649c08f src: Use of device_t is deprecated
Change-Id: I9cebfc5c77187bd81094031c43ff6df094908417
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14 09:29:31 +00:00
Raul E Rangel 846b4941fe stoneyridge: Increase SMM stack size to 2K
GSMI Set Event Log is taking more than 1K in stack. This causes the
stack to overflow into the adjacent stack. This has the side effect of
causing any CPU waiting for the SMI handler to complete to crash when
the lock is unlocked because the return pointer has been smashed.

BUG=b:80539294
TEST=built on grunt and tested by running `halt` from the OS.

Change-Id: Ib170c7d03909ef3d20831726b285178a75007b06
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27033
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14 09:29:04 +00:00
Raul E Rangel d3b8393310 cpu/x86: Make SMM stack size configurable
Stoneyridge is running into a stack overflow in the SMM handler.

BUG=b:80539294
TEST=built on grunt

Change-Id: I94e385497bd93c3638c69fb08d9b843c3bbb55ce
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27034
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14 09:28:45 +00:00
Nick Vaccaro f0afb3e335 mb/google/poppy/variants/nocturne: config GPP_E2 for BT_DISABLE_L
GPP_E2 will be used as a BT reset line, so configure GPP_E2 as an
output and initialize it high (high = out of reset).

BUG=b:80089559
BRANCH=none
TEST=none

Change-Id: If45ef3a592c389a0b80298c59eea849d07d9671e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-14 09:27:48 +00:00
Nick Vaccaro fc7cc42813 mb/google/poppy/variants/nocturne: config GPP_B4 for FCAM_PWR_EN
FCAM_PWR_EN signal is changing to connect to GPP_B4 instead of
GPP_D8 as it needs a 3.3v gpio to provide enough power to also
directly power the camera LED.

BUG=b:79667559,b:78122599
BRANCH=none
TEST=none

Change-Id: Ie875ced45dfa2aa7069851004edde8f77329df34
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-06-14 09:27:39 +00:00
Cole Nelson 9d0950f154 soc/intel/{glk,apl}: ensure C1E is disabled after S3 resume
C1E is disabled by the kernel driver intel_idle at boot.  This does not
address the S3 resume case, so we lose state and C1E is enabled after S3
resume.

Disable C1E for GLK as it is for APL.  This gives a coherent state before
and after S3 resume.

TEST='iotools rdmsr cpu 0x1fc'. Returns the same value after boot and S3
resume with bit [1] set to zero (0x20005d).

Change-Id: I437cbaca75c539c2bc5cd801ab8df907e7447d10
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/27019
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14 09:26:27 +00:00
Cole Nelson 2b69b21c2d soc/intel/common: defines constant for C1E enable mask
Register 0x1fc (MSR_POWER_CTL) deserves a proper mask for the C1E
enable bit.  Define POWER_CTL_C1E_MASK to be used subsequently.

Change-Id: I7a5408f6678f56540929b7811764845b6dad1149
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/27035
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14 09:25:57 +00:00
Patrick Rudolph c38960d7f3 lib/device_tree: Add method to get phandle
Add a method to retrieve a node's phandle.
Useful for board specific devicetree manipulations.

Change-Id: I966151ad7e82fc678ab4f56cf9b5868ef39398e0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-14 09:25:41 +00:00
Patrick Georgi 79d26c7a83 util/docker/coreboot.org-status: collect report generators
Move generators for the board status report and the kconfig options
report into a common directory and wrap them in a docker container.

Also rework to emit HTML not wiki syntax.

Change-Id: If42e1dd312c5fa4e32f519865e3b551bc471bc72
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-14 08:45:24 +00:00
Martin Roth 31e0d42a1d util/lint: Run lint-extended-007-final-newlines checks in parallel
Instead of checking each directory in series, kick off the checks
in parallel and then wait for them to finish.  Failures print out with
file information, so mixing output isn't a problem.  This reduces
the time it takes to run on lumberingbuilder by 60%.

This could probably be sped up even more by splitting up src/mainboard
into smaller sections.

This method does skip a few control files at the top level - .gitignore,
.checkpatch.conf, gnat.adc, etc.  These could be added to the list of
files to check, but I didn't think it was needed.

Change-Id: I171977e713a9956cf4142cfc0a199e10040abb35
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14 08:42:30 +00:00
Kyösti Mälkki 1dc5ce31ce coreinfo: Skip unpopulated PCI functions
Per PCI specification, function 0 must be present,
so functions 1 to 7 can be skipped in this case.

For a device that is not multi-function, it may not
decode function number in the hardware at all. To
avoid registering such a device eight times, skip
scanning functions 1 to 7.

Without the latter fix, a single-function PCI bridge
may call pci_scan_bus() second time and secondary
side devices would get appended second time in the
array devices[]. At that point, quicksort() apparently
hits an infinite recursion loop.

Since pci_scan_bus() is called in part of the early
modules->init() sequence early in main(), the errors
here left coreinfo payload completely silent when
PCI module was built-in on affected system.

Terminal screen was cleared, though.

Change-Id: Ifc6622f050b98afb7196de0cc3a863c4cdfa6c94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-14 07:59:05 +00:00
Kyösti Mälkki 3414f6035b AGESA binaryPI: Drop RAMBASE and RAMTOP
With platforms moved to RELOCATABLE_RAMSTAGE, these
overrides no longer have a meaning.

Overrides existed because AGESA ramstage did not fit within
the default 1 MiB of RAMTOP - RAMBASE, when placed low.

Change-Id: I0185875dc550de74877c94f36128d5979e5553d6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26813
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14 07:25:29 +00:00
Kyösti Mälkki 58175c7010 AGESA binaryPI: Drop tests for LATE_CBMEM_INIT
Change-Id: I4571e8b560559b3d7afe429eca8caa1512e244a8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-14 07:24:35 +00:00
Marshall Dawson c4be175bdc amd/stoneyridge: Add early MTRR setup for new callouts
Enable the two ranges to be used for the new callouts, AgesaHeapRebase
and AgesaGetHeapBaseInDram.

TEST=Boot grunt w/experimental blob, try different addresses
BUG=b:74518368

Change-Id: Ic7716794dc7d75f849e6e062865d6efbeb4292df
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/26147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-13 21:21:19 +00:00
Marshall Dawson c150a57d29 amd/pi: Add AgesaHeapRebase callout
Implement an optional callout for AgesaHeapRebase which allows AGESA
to override any internal hardcoded heap addresses.

Designate a region in CAR that may be used for pre-mem heap and return
that address before DRAM is configured.  After DRAM is up, the address
in cbmem is returned.

TEST=Boot grunt with patchstack and experimental blob
BUG=b:74518368

Change-Id: Ieda202a6064302b21707bd7ddfabc132cd85ed45
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-13 21:21:09 +00:00
Marshall Dawson 10b52e0f22 amd/pi: Add GetTempHeapBase callout
Implement a new AGESA callout that may be used to find the correct
temporary location in DRAM to store heap data.

Near the end of AmdInitPost, AGESA migrates its heap from a CAR-based
location to a temporary region.  Once cbmem has been established, the
heap will be relocated again in AmdInitEnv from the temp location to
the final one.

This patch does not materially affect the behavior of AGESA's heap
management.  It only puts coreboot in control of the location.  Future
work may refactor the copying.

TEST=Boot grunt with patchstack and experimental blob
BUG=b:74518368

Change-Id: Ibc5cc988e3e80d78f50cf0195e952b657141e570
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/26146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-13 21:20:41 +00:00
Marshall Dawson 669ba23710 vc/amd/00670F00: Sync AGESA.h with PI blob
Add a new callout definition for AgesaGetTempHeapBase and displace
AgesaHeapRebase (which was merged too soon) in the ordering.  Also
add its structure.

AGESA will be modified to ask coreboot for the location for temporary
storage of heap data at the end of InitPost.  The old methodology is
to use 0xb0000 but the change will allow coreboot to determine the
location.

BUG=b:74518368

Change-Id: I0bc894d7842cf4b3eb728a90704277b17f4bf7be
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/26145
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-13 21:20:32 +00:00
Patrick Rudolph 7a2a29d0e1 Documentation: Add rules for writing Documentation
Change-Id: Ic3808a0a10ddc8064d185e0920dcd9f60c435419
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-13 17:43:20 +00:00
Angel Pons 16c77f72ca src/mainboard/*: Remove empty vendor folders
After removing most geode_lx boards, some mainboard
directories are left empty. This patch cleans them up.

Change-Id: I2e99eba3d49dec90ceb2ce0c7f61612a9840ce59
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/27092
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-13 15:14:20 +00:00
Nicola Corna 364f2e10cb sb/intel/common/firmware: Use the -S flag of me_cleaner
The -S flag of me_cleaner, in addition to the standard code removal,
sets the the AltMeDisable bit (ME 6.x-10.x) or the HAP bit (ME 11.x),
which asks Intel ME to stop the execution after the hardware
initialization.

This should bring some advantages:
 * The state of Intel ME can be easily obtained by reading the Current
    Operation Mode register to trigger specific adjustments in the
    raminit (as already done in bd82x6x)
 * Intel ME falls into a more defined state, instead of being in a
    generic "Image Failure"
 * Hopefully, less code is run by Intel ME, as the execution should
    stop before even trying to load additional modules

Tested on:
 * Nehalem, Sandy Bridge and Ivy Bridge (Nicola Corna)
 * Broadwell, Skylake and Kabylake (Youness Alaoui)

If needed, the -S flag can be removed or integrated with other
board-specific options by overriding CONFIG_ME_CLEANER_ARGS.

Change-Id: I2c12d09124dcc39924d1dc4eaf53a2dc1f69a2ac
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/25508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2018-06-13 14:49:00 +00:00
Furquan Shaikh de39fc7160 util/sconfig: Prepare sconfig to allow parsing multiple trees
In preparation to allow devicetree overrides, it will be necessary to
use the same parsing functions to prepare two separate parse
trees. This change does the following things:
1. Updates root device and bus names to add base_ prefix.
2. Adds a function parse_devicetree that sets the root_parent and
linenum before calling yyparse().
3. Updates all uses of root_dev to refer to the next base_root_dev.

BUG=b:80081934
TEST=Verified that static.c generated for all boards built using
abuild is the same with and without this change.

Change-Id: I403a90c1ebf07ac66115ddfe137daf0980dc1a18
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-06-13 14:48:12 +00:00
Richard Spiegel 93459d6278 soc/amd/stoneyridge/acpi.c: Create GPIO acpigen procedures
There are some acpigen functionality that have not been implemented. They
are defined as week within acpigen.c, in order to not break the build.
This adds stoneyridge specific versions.

BUG=b:79546790
TEST=Build grunt with added debug code to gpio_lib.asl. Boot to OS,
activate ACPI debug, activate S3 stress test. Interrupt stress test, do a
"cat /var/log/messages" saving the serial output. Examine the serial
output, see added debug code showing action taken. Confirm action by
reading proper register. Debug code removed.

Change-Id: I9062d889f828a3175b89e6f4a3659ebbf90eac68
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-13 14:24:42 +00:00
Richard Spiegel 572f4988dd soc/amd/stoneyridge/southbridge.c: Fix saving _SWS parameters
PM1 and GPE0 are being stored directly to NVS, when actually what should
be saved is the index of the bit responsible for waking. Fix the procedures
and add definitions to the actual IO addresses to be read when recording
status and enable registers.

BUG=b:75996437
TEST=Build and boot grunt. Once in OS, execute a sleep and a wake. See the
message indicating which indexes are being save in NVS for _SWS. Try sleep
stress test, verify that the index is different from that of power button.

Change-Id: I8bafc7bb7dd66e7f0eb8499e748535bbdcac5f53
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-13 14:24:31 +00:00
Richard Spiegel 9b05af367f soc/amd/stoneyridge/acpi: Create a GPIO library
There are some acpigen functionality that have not been implemented. In
order to implement them, ACPI GPIO functions to read and write to the
control MMIO of a particular pin is needed. So as a preliminary task to
implementing acpigen functions, create a library with functions to be
accessed by acpigen generated ACPI code.

BUG=b:79546790
TEST=Build grunt, more tests with commit 0f2acbd6b1.

Change-Id: I21c014b7f2698dd9193dae3113b18ee2a7303bcf
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-12 21:15:16 +00:00
Nico Huber 29cc33181a drivers/intel/gma: Unify VBT related Kconfig names
Shuffle words and drop the _DATA_FILE suffix.

Change-Id: I0b0d50ea729e5580c0bc7b43f250ff387ce59cfc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-12 18:07:51 +00:00
Raul E Rangel 873b4e70bc stoneyridge: Move agesa out of bootblock
This is Garrett's patch with a bit of cleanup.

BUG=b:65442212
TEST=Was able to boot, suspend and resume on grunt.

Change-Id: I55959b59a4e60b679d959ebd77de27e5d454f5f7
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/26478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-12 18:04:52 +00:00
Martin Roth f1eff68ef5 util/lint: Run lint-extended-007-checkpatch checks in parallel
Instead of checking each directory in series, kick off all the checks
in parallel and then wait for them to finish.  Failures print out with
file information, so mixing output isn't a problem.  This reduces
the time it takes to run on lumberingbuilder from 31 seconds to 6.

Change-Id: I1252a68a723370389d399f3d1a2aff3fad64c365
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-12 11:11:54 +00:00
Furquan Shaikh 24681f188a drivers/i2c/generic: Ensure config is not NULL before accessing it
This change checks to ensure that config is not NULL before it is
accessed for the first time.

Reported by: Coverity CID #1393312

Change-Id: Ic248c79783da9c2bfdf3b7f737e5963feff7558c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-06-12 11:11:42 +00:00