If this bit is set, ich7 will enter C4 mode if possible instead of
C3. See ich7 specification (LPC controller, Power management control
registers) for more details.
Change-Id: I352cccdbc51ff6269f153a4542c7ee1df0c01d22
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/329
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Correct a typo in devtree.asl which causes AML processors to fail executing
the DSDT with AE_NO_MEMORY or (in case of acpiexec) Divide By Zero.
Also removes an superfluous item in the register IndexField and removes
unneccessary _PR0 definitions which could confuse AML processors.
Change-Id: I02cb9ce4e8f2101cfff8cec4abba7e070fd66364
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/296
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Logic is inverted (if argument is true, one would expect that
mute is enabled) and the wrong bit was used (1 instead 0)
Change-Id: I71133ba639f1fb0d3c3582f16211dd266a11cc64
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/334
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
muting is handled by h8 code, no need to do it here.
Change-Id: I3f152e99f30701cd032b03105cbe3ae778865305
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/335
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Doing it this way will break all subsequent smbus calls, because
the smbus code still uses res->base, which points to the old base
address. Fix this by allocating a proper resource.
Change-Id: I0f3d8fba5f8e2db7fe4ca991ef2c345aff436ea4
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/325
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Tested-by: build bot (Jenkins)
This fixes the build for HEAD/master.
Current stable will not work, because it is too old for recent corboot.
Change-Id: I9dfd5de472d4f58f07147cb9b9bb0b543f228561
Signed-off-by: Thomas Gstädtner <thomas@gstaedtner.net>
Reviewed-on: http://review.coreboot.org/311
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The xgcc toolchain may be moved by the user and passed in on the commandline. Updates the Makefile and the xcompile script.
Change-Id: I05797b2cabce39bdd7868c2515f30d34043fc8cc
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/318
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Add a configuration option POST_PORT which defaults to 0x80 and
can be redefined by boards which have integrated POST displays
on another I/O port. Change post.c to output POST codes to this
port instead of 0x80 hardcoded.
Change-Id: I8f8e820f8c75641b35e7249bf622b63a3604b9f3
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/221
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Add configure option SB_GPP_UNHIDE_PORTS for mainboard
to hide/unhide the unused sb800 gpp ports.
Certain gpp port should be hidden, if no device was detected and
hotplug feature is disabled for such port.
Hidden unused ports makes lspci -vvv get more accurate information under Linux.
Test on avalue/eax-785e mainboard.
Change-Id: I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/207
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Add information about memory mapped/io mapped base addresses.
and fix up libpayload to use the same structures
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: I5f7b5eda6063261b9acb7a46310172d4a5471dfb
Reviewed-on: http://review.coreboot.org/261
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit replaces the old svn checkout code for the external FILO
payload with a git checkout for the new repo on gerrit.
The stable checkout is implemented similarly to the former SVN variant,
it checks out a specific commit (same commit as svn r136 which was
checked out before).
The HEAD checkout gets the master branch from
http://review.coreboot.org/p/filo.git
In future this should probably be changed to a stable tag or repo.
It is necessary to remove the old svn checkout by hand (or run
distclean), because I did not include code to remove an existing svn
FILO checkout.
Change-Id: I08a703f3428ae7b987f7079a4901be4cf6d7e505
Signed-off-by: Thomas Gstädtner <thomas@gstaedtner.net>
Reviewed-on: http://review.coreboot.org/308
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Time for the brown paper bag: OHCI controllers are not happy when
told to send data, but with obviously wrong addresses. It helps
to write the addresses into the data structures.
Change-Id: Ic0967dc8939e64af119cfb89400a045a2c077171
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/306
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This was mentioned several times already, how about we get it in?
It avoids cbfstool to fail because path/to/"file" doesn't work.
Change-Id: Ia01acbd78f81a5db890fd1573a2f3cbe1450562f
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/305
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
also clean out a local copy of ntohl in yabel.
Change-Id: Iffe85a53c9ea25abeb3ac663870eb7eb4874a704
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/288
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Those modules have basically the same Super I/O capabilities as
the Docking station. Unfortunately, the Super I/O in the module
shares the same I/O address as the Docking station, so we're not
allowed to connect the LPC Docking Bus if such a module is present.
To be able to detect this device and use it as early console for
coreboot, we have to initialize the GPIO Controller before, as
this device is detected via GPIO06.
Change-Id: If7c38bb6797f76cf28f09f3614ab9a33878571fb
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/282
Tested-by: build bot (Jenkins)
Patch is required to compile this with romcc.
Change-Id: I5c4c0f5b32e5edeb8c48d8455b3493ca79f8b452
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/291
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
This makes the power_on_after_fail NVRAM option work correctly.
Change-Id: I96f05f82d7f133b343cf8d4ef09db50a3db7a83d
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/292
Tested-by: build bot (Jenkins)
and add drivers/generic/generic back (empty), since it is used by many
devicetree.cb files.
Without this patch typos in component names in devicetree.cb cause
the component to be silently ignored.
Change-Id: I3cfca2725816f0cd7d72139ae53af815009e8ab4
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/270
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
That's what SeaBIOS does, too, and it works just fine.
Change-Id: I3e17c15848aca86f775fc86f4ad906c820625887
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/269
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
config.h defines also unset config options (as "0") so #ifdef
matches both settings, which isn't what we want.
Change-Id: I694e1b8a8ec4c20225d7af1a13a2a336f900e643
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/293
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
A mainboard may require configuration of the superio pins to fully
support some features. Things like A20# gate, leds, fans, infra-red
and bootstrap jumpers may be configured and controlled through the
logical PME device.
Change-Id: I6e77ff0295806ba3dff339013f73d99c2961388f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/289
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
As new microcode files were included, the table was not updated with
families 0f25 and 0f26.
Change-Id: I5bb8be9d7c37eb8406dcb48a4b933eab24639bda
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/290
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Our cmos checksum is inverted to what the Linux /dev/nvram device expects (and
BIOSes use). This makes it impossible to use /dev/nvram with coreboot. Fix it!
Change-Id: I239f7e3aca05d3691aee16490dd801df2ccaefd1
Signed-off-by: Vadim Bendebury <vbendeb@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/279
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Also add a meaningful define (Not hooked up in Kconfig, that might
or might not follow)
Change-Id: I9cc4bca0d23d75e6a1d767932ec62e8c68b39d71
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/278
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
If a file can't be added by cbfstool, print the type and name of the file
in the error message.
Change-Id: I369d6f5be09ec53ee5beea2cfea65a80407f0ba3
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/271
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
After a lot of experimentation this commit improves some hardware
features that were not recognized or incorrectly configured before.
The only thing not tested is SCSI-option board (I dont have one).
Misleading errors in comments have been corrected.
(Note BTW that the DL145 G1 mainboard is identical to AMD Serenade
which was supported in early versions of coreboot but was dropped
for some reason.)
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Change-Id: Ibbd97fafad22196b1e18d0b257731490339f113e
Reviewed-on: http://review.coreboot.org/237
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
First issue fixed:
For multi-socket CPU the current implementation emitted
Processor objects for cores in the first CPU only. This
commit fixes the bug by really emitting one Processor
object for each core. However, the unlikely case of mixed
CPU models is still not handled correctly.
Second issue fixed:
One loop was wrong in case a processor in the table declares
no P-states at all. The rewritten loop is safe. Some possibly
dangerous array lengths were also fixed.
Third issue: on MP-boards the recommended ramp-voltage (RVO) is 0mV
according to the BKDG. The current implementation always set it
to 25mV. This commit selects 0 or 25mV depending on CONFIG_MAX_PHYSICAL_CPUS.
Fourth issue: If a processor without PowerNow! support was inserted in a
system with coreboot configured with SET_FIDVID then the boot process hanged
mysteriously and very early. Apparently because init_fidvid_ap tampers with
non-existing registers. This commit fixes the bug by bailing out
from init_fidvid_ap if PowerNow! capability is missing.
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Change-Id: I61f6e2210b84ccba33a36c5efc866447b7134417
Reviewed-on: http://review.coreboot.org/239
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
According to Rudolf Marek putting a memory instruction between
the CR0 write and the jmp in protected mode switching might hang the
machine. Move it after the jmp.
There might be a better solution for this, such as enabling the cache, as
keeping it disabled does not prevent cache poisoning attacks, so there is no
real point.
However, Intel docs say that SMM code in ASEG is always running uncached, so
we might want to consider running SMM out of TSEG instead, as well.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: Id396acf3c8a79a9f1abcc557af6e0cce099955ec
Reviewed-on: http://review.coreboot.org/283
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Tested-by: build bot (Jenkins)
It's only used in cbfs_and_run.c
Change-Id: Ibcfcefbeb0c5722eb3888f0d60127229a2badcf6
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/273
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
Sven Schnelle