The headers added are generated as per FSP v2385_02.
Previous FSP version was 2376.
Changes Include:
- add VtdIopEnable, VtdIgdEnable, and VtdIpuEnable UPDs in Fspm.h
TEST=Build and boot JSLRVP
Change-Id: I268eca1bcbbf26d4dc4ecf54d432cdb6ad49b4eb
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47500
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds details about the new resource allocator v4 in
coreboot to the release notes for 4.13.
Change-Id: I7071bdf0faffda61fc5941886c963181939c07e3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The current HID "RX6110SA" does not comply with the ACPI spec in terms
of the naming convention where the first three caracters should be a
vendor ID and the last 4 characters should be a device ID. For now
there is a vendor ID for Epson (SEC) but there is none for this
particular RTC. In order to avoid the reporting of a non ACPI-compliant
HID it will be dropped completely for now.
Once Epson has assigned a valid HID for this RTC, this valid HID will be
used here instead.
Change-Id: Ib77ffad084c25f60f79ec7d503f14731b1ebe9e2
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47706
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It was supposed to return true for both S2 and S3, but
level S2 was never stored in acpi_slp_type or otherwise
implemented.
Change-Id: Ida0165e647545069c0d42d38b9f45a95e78dacbe
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
By renaming the AMD SOC common Kconfig file the wildcard to source all
AMD SoC-specific Kconfig files won't match to it and it can be sourced
after all SoC-specific Kconfig files in the sub-directories are sourced.
This change allows adding new SoCs without having to edit the soc/amd
Kconfig file.
Change-Id: Iaaa5aad23eb6364d46b279101f3969db9f182607
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Extend the Kconfig option text of L140CU with L141CU since the hardware
of both is equal.
Change-Id: If0e5061fc345208688a678a4cdf7c5ecaf47c17d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Volteer has a new Audio option in FW_CONFIG. This patch adds
support for it and when enabled, programs GPIO pins for I2S
functionality.
BUG=b:171174991
TEST=emerge-volteer coreboot
Change-Id: I85bc37980957a3fb6c795858a4e4f44f3e3cc332
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Ambassador is similar to puff. This change matches the
PcieRpSlotImplemented configuration with Puff's, originally made for
Puff in https://review.coreboot.org/c/coreboot/+/39986.
Signed-off-by: Matt Ziegelbaum <ziegs@google.com>
Change-Id: I5b6246f58c10e03a0d02278ad3621ded39bb6d6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Fan table: provided by the ODM (see attachment in bug) based on
measurements with EVT unit.
BUG=b:173134210
TEST=flash to DUT
Change-Id: I9f727f0f7e2eb7fe70385ebc843558d51e1860c5
Signed-off-by: Matt Ziegelbaum <ziegs@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Different models within family 17h have different PCI IDs for their PCIe
GPP port and internal bus devices.
Change-Id: I386df908ce5451b4484be2a2e4a9018c3d47d030
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Different models within family 17h have different PCI IDs for their data
fabric PCI devices.
Change-Id: I44f8d32c950710e962dc519495b08c92f357ed20
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The code that uses the GPU device ID uses the correct ATI vendor ID, but
the description wrongly used AMD as vendor. In the AMD APUs the GPU PCI
device and the corresponding audio controller use the ATI PCI vendor ID
while all other PCI devices in the SoC use the AMD PCI vendor ID.
Also move the two entries in a separate section right below the one they
were in.
Change-Id: Ia0b5bd4638f5b07c487f223321872563b36337e9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
SOC_AMD_COMMON needs to be selected to be able to select
SOC_AMD_COMMON_BLOCK which only includes the Kconfig files from the
function block sub-folder. Removing SOC_AMD_COMMON_BLOCK and the
corresponding Kconfig file and make SOC_AMD_COMMON include all Kconfig
files from the sub-folders simplifies this a bit.
Change-Id: I9068d57a80bdc144e73d2b8c00e7b2cae730d4b6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Drop extra function in the middle and adjust the post_code()
to happen right before jump to wakeup vector.
Change-Id: I951c3292f5dbf52a58471da9de94b0c4f4ca7c20
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42613
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SMSC/Microchip 1036 can be strapped to 4E/4D and 164E/164D so make
source code support 16 bits addressing.
Change-Id: I2bbe6f5b6dbd74299b34b0717e618dc736e7ad6f
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Configure the pins for SD to msdc1 mode and change the driving
value to 8mA. Enable VCC and VCCQ power supply for SD.
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Change-Id: I11151c659b251db987f797a6ae4a08a07971144b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
SD Card driver needs to access two regulators - MT6360_LDO5 and
MT6360_LDO3. These two regulators are disabled by default.
Two APIs are implemented:
- mainboard_enable_regulator: Configure the regulator as enabled/disabled.
- mainboard_regulator_is_enabled: Query if the regulator is enabled.
BUG=b:168863056,b:147789962
BRANCH=none
TEST=emerge-asurada coreboot
Change-Id: I391f908fcb33ffdcccc53063644482eabc863ac4
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46687
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
google_chromeec_regulator_enable is for enabling/disabling
the regulator. google_chromeec_regulator_is_enabled is for
querying if the regulator is enabled.
BUG=b:168863056,b:147789962
BRANCH=none
TEST=emerge-asurada coreboot
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Ia804242042b0026af19025a0c4a74b3ab8475dab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Currently, five regulator controls are implemented for DRAM
calibration and DVFS feature.
The regulators for VCORE and VM18 are controlled by MT6359.
The reguatlors for VDD1, VDD2 and VMDDR are controlled by MT6360
via EC.
BUG=b:147789962
BRANCH=none
TEST=verified with DRAM driver
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Id06a8196ca4badc51b06759afb07b5664278d13b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
MT8192 uses power management interface (PMIF) to access pmics by spmi
and spi, so we add pmif driver to control pmics.
BUG=b:155253454
BRANCH=none
TEST=boot asurada correctly
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: I32fc28f72d9522133baa06f9d67c383f814d862c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45398
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This function is no longer required to be implemented since
EC/AUXFW sync was decoupled from vboot UI. (See CL:2087016.)
BUG=b:172343019
TEST=Compile locally
BRANCH=none
Signed-off-by: Joel Kitching <kitching@google.com>
Change-Id: I43e8160a4766a38c4fa14bcf4495fc719fbcd6c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The current CSE firmware update implementation adds CSE RW binary to
FW_MAIN_A/B and this increases the boot time due to the size increase
of these regions leading to higher loading and hashing time.
To mitigate this issue, CSE RW binary is moved from FW_MAIN_A/B to new
region, ME_RW_A/B under RW_SECTON_A/B, and this updates the flashmap to
add ME_RW_A/B region for CSE RW binary.
BUG=b:169077783
TEST=build with cse rw binary, flash and verify volteer2 boots to OS.
Verify me_rw binary is added to ME_RW_A/B region.
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I87da3824933ed2dd8e8ed0fed8686d2a3527faea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46431
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CSE RW blob which will be used by coreboot to update CSE's RW partition,
is packed part of FW_MAIN_A and FW_MAIN_B. This will increase the size of
FW_MAIN_A and FW_MAIN_B. So, accordingly load and hash calculation of
FW_MAIN_A (or FW_MAIN_B) increases during verstage. It increases the boot
time by around 300ms.
The patch address the boot time by pulling CSE RW blob outside of
FW_MAIN_A and FW_MAIN_B. So, it creates new FMAP region within
RW_SECTION_A and RW_SECTION_B and adds CSE RW blob in the new regions
(ME_RW_A and ME_RW_B) as a CBFS file.
Boot Time Measurement details when CSE RW blob is added in the
ME_RW_A and ME_RW_B.
--------------------------------------------------------
| Platform | Old Boot Time | New Boot Time |
--------------------------------------------------------
| JSL | 1.3s | 1.06s |
--------------------------------------------------------
| TGL | 1.63s | 1.36s |
--------------------------------------------------------
Changes:
1. Makefile change to accommodate CSE RW blob into ME_RW_A/ME_RW_B
2. Kconfig change to define CBFS name and default file name for RW blob
metadata.
3. CSE Lite Driver
BUG=b:169077783
TEST=Verified on JSL & TGL platforms
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: If043c9cb99fb822b62633591bf9c5bd75dfe8349
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This patch modifies flash layout to add ME_RW_A/B to add
the CSE RW blob and also enable the CSE RW update feature for
JSLRVP
BUG=b:169077783
TEST= Built for jslrvp. Verified that CSE RW and metadata files
are included in cbfs.
Change-Id: I13baa317a06d00cec0337f08754892c7c8737f5d
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Existing implementation adds the CSE RW update binary to FW_MAIN_A/B
regions and this has significant impact on boot time due to the
increase in the size of these regions leading to higher loading
and hashing time.
This patch modifies flash layout to add new ME_RW_A/B fmap regions
in the RW_SECTION_A/B.
BUG=b:169077783
TEST= Built for dedede. Verified that CSE RW binary is added to the
CSE_RW_A/B fmap region.
Change-Id: I23a3e22a569488b39beb4d12f5b6309c7c742992
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In the existing implementation CSE RW metadata file is generated by
scripts and to avoid incompitable issues between coreboot and the
scripts this patch adds the follwing changes,
* Move the metadata generation to the coreboot Makefile.
* Add CBFS component type struct to create a metadata file during
the compile time.
* Extract the CSE RW version from SOC_INTEL_CSE_RW_VERSION config
and update the major, minor, hotfix and build versions using the
compile time flags.
* Compute the hash of CSE RW binary in hex format using the openssl
and use the HASH_BYTEARRAY macro to convert the 64 character hex
values into the array.
* Add the me_rw.metadata cbfs file to FW_MAIN_A and FW_MAIN_B
regions.
BUG=b:169077783
TEST= Built for dedede. Verify that metadata file was generated
and added to the FW_MAIN_A/B. Extracted it using cbfstool and
verfied that metadata was generated properly.
Change-Id: I412581400a9606fa17cf4398faffda923f07b320
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add the Kconfig to enable the CSE FW Update feature and also to
ensure all the configs are set by the mainboards to enable this
feature.
This config by default disables the CSE FW update feature for JSL
and TGL platforms. It will be enabled after splitting and including
the CSE RW and CSE RW metadata blobs in the CBFS.
BUG=b:169077783
Change-Id: I12810031224f79aba8a4057725ae0ed5a9b36d7e
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This patch adds a kconfig SOC_INTEL_CSE_RW_VERSION to pass the
CSE RW firmware version from the mainboard. This will be extracted
by makefile to update the cse_rw_metadata structure.
Right now the required tool to extract the CSE RW version from
the blob is still under development and after the official version
of the tool is released, version will be extracted by parsing the
CSE RW blob.
BUG=b:169077783
Cq-Depend: chrome-internal:3402224, chrome-internal:3397863,
chromium:2473603, chromium:2473603, chromium:2535950
Change-Id: I62691ee3ede7d4cd21f821381f5d1519f9061fd9
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47430
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SKX FSP doesn't support X2APIC setup, but CPX does. The CPX DMAR
table needs the X2APIC opt out flag set. This fixes the hang loading
a kexec'd kernel. The change is easy to see in the coreboot output:
[DMA Remapping table] Flags: 0x3
or in the DMAR ACPI table.
Change-Id: Iec977c893b70e30875d9a92f24af009c1e90389e
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
When the system shuts down, turn the fingerprint sensor off. This sets
the GPIOs correctly for the next boot. The fingerprint sensor was
previously left on, and was just powering down when the rails went low.
On suspend, the fingerprint sensor stays awake and puts itself in a low
powerstate mode based on the SLP_Sx_L pin states.
BUG=b:171837716
TEST=Fingerprint sensor still works after S3, GPIO state on the boot
following a shutdown is low.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I3837b58372d8f4a504535e76bd21c667d68f8995
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47311
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
At this point, the zork platform will only use psp_verstage, so remove
the VBOOT_STARTS_IN_BOOTBLOCK option and set code for VBOOT_STARTS-
BEFORE_BOOTBLOCK to always be used.
TEST=Build & Boot Morphius
BRANCH=Zork
BUG=b:172848137
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I30d90fe82c37966a860b52c07a3550dcecf8d19d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This partially reverts commit 67910db907.
The symbol X86_RESET_VECTOR continues to live, for the time being,
under soc/amd/picasso.
Change-Id: Ib6b2cc2b17133b3207758c72a54abe80fc6356b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This change drops the inclusion of entry16.ld and reset16.ld and
instead adds the content of those files directly in memlayout_x86.ld
in amd/picasso. This is done to allow the work for top-aligning
bootblock to happen independent of Picasso layout. Once that is
complete, Picasso layout can be re-evaluated to see if it can make use
of the common bootblock linker file includes.
TEST=Verified that coreboot.rom generated using --timeless is the same
with and without this change for trembyle.
Change-Id: Ib1218b24a06d0f69b856fb21458a6183fd21fcbc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The current I2C2 bus frequency is 344 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C2 to bring
the bus frequency closer to 400 kHz.
BUG=b:153588771
TEST=Verified that I2C2 frequency is 380 kHz.
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: I96fa5ed586de41324733ac7537b6bd73f39fc176
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47558
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ronak Kanabar