The name is derived directly from the device path.
Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
The includes removed here were previously required for
struct lb_memory and lb_add_memory_range().
Change-Id: Ie6c0d4ef55c2225aa709cf3fbad30ff1080e3610
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1391
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
These existed to provide a hook to add reserved memory regions
in the coreboot memory table. Reserved memory are now
added as resources.
Change-Id: I9f83df33845cfa6973b018a51cf9444dbf0f8667
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1414
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Use of lb_add_memory_region() is reduntant with the MMCONF
resource being set as reserved.
Change-Id: I747ea34823692b6966b2e50d22aea1fb89c73c25
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1394
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The function is a noop for all but amd/serengeti_cheetah.
Change-Id: I09e2e710aa964c2f31e35fcea4f14856cc1e1dca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1184
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Move beep commands to board-specific area as they need to be different for
different codecs.
Change-Id: I2a1ac938c49827cc816a95df10793a7e234942bf
Signed-off-by: Dylan Reid <dgreid@chromium.org>
Reviewed-on: http://review.coreboot.org/1410
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Move the POST display to take place just before jumping
the payload, a bit later than before.
Change-Id: Ie1d1ff24dc6c1640e25681be7dc5740943c7f112
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1396
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The board had HAVE_MAINBOARD_RESOURCES=0 so this was never
called. Drop unnecessary includes too.
Change-Id: Ia7bddf29a16966c052b5cabbb47029299e6dbd12
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1392
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Commit 188e3c2ff0 dropped mainboard
out of the static device tree. This left dev_root->chip_ops unset,
and mainboard_ops.enable_dev() was no longer called.
Change-Id: I6d447c8049a66041b8bb36ec9aac3e7e0d20a99b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1374
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Thatcher features: Family 15 trinity FP2. Hudson.
close to Parmer.
This board and parmer both need to revert the change
http://review.coreboot.org/#/c/1359/, and add thatcher's own
chip.h,otherwise the mainboard_enable can not be called.
Change-Id: I54e1cfca845fbcea1d3aad5eff08d760d0d215c9
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1382
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
UMA region can be determined at any time after the amount
of RAM is known and before the uma_resource() call.
Change-Id: I2a0bf2d3cad55ee70e889c88846f962b7faa0c7e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1379
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Use of uma_resource() in northbridge code created a memory
resource marked as reserved. Such resources are removed
from system memory in write_coreboot_table().
Change-Id: I14bfd560140d8d30ec156562f23072bfae747bde
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1238
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
This reverts commit 78efc4c36c.
The broadcast patch was reverted, so this commit should also
be reverted. The reason for reverting the broadcast patch:
It turned out that sending IPIs via broadcast doesn't work on
Sandybridge. We tried to come up with a solution, but didn't
found any so far. So revert the code for now until we have
a working solution.
Change-Id: I05c27dec55fa681f455215be56dcbc5f22808193
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1380
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
mainboard_config never worked right, at least not since we've had sconfig.
Hence, drop mainboard/<vendor>/<device>/chip.h and fix up the mainboards that
tried to use it anyways.
Change-Id: I7cd403ea188d8a9fd4c1ad15479fa88e02ab8e83
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1359
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
LX has two values that are usually automatically derived but can
be overridden, that were so far defined in each board's romstage.
These values, along with the toggle to enable override are now
part of LX's Kconfig. For boards that gave values but requested
autogeneration, the values are removed.
Further improvements: Figure out the various fields in PLLMSRlo
and make them sensible Kconfig options (instead of the hex value
it is now)
Change-Id: I8a17c89e4a3cb1b52aaceef645955ab7817b482d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1227
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Read event routine didn't get the correct BIOS callout. So it could not get
the heap address. Then it would creat many warning in serial port.
Change-Id: Ia35601bda1579c7f726ed767d7be78713ac185d2
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1266
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The board has a marvell NIC, but the driver to disable NIC BIOS was adapted
from a Realtek 8168 driver. Rename to reflect the change.
Also hook up as driver, so coreboot can actually find it.
Change-Id: Ibdfd6074eb28ba537d68552a3346b06493cef2a6
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1355
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
One copy was slightly different, but all the differences were commented out
Change-Id: I3cc7b5621c681a1eb286f9b16ef3ebdce03abb6b
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1356
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is for GfxInitSview(GnbSview.c). It would create warning message if it
could not get VBIOS image.
Change-Id: I3b2726f612b4b7a237644a4b63b56efad52b7ab5
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1351
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Remove the warning message from linux dmesg,
mtrr: your BIOS has configured as incorrect mask, fixing it.
Change-Id: I355509db12ab10c33b7c1c23e2c7c4783f30e67e
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1349
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The function acpi_get_vdat_info() was moved to the ChromeOS
vendor code, and is no longer required to be present for each
board. Hence, remove it.
Change-Id: I3dc8dbb6119ceffa057373bad7c0058ac0d40eb8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1283
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The function is empty (a left-over from i945) and should be removed.
Change-Id: I91e573b5e37cb9133ea1037aef7e6daf3c292864
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1290
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This enable step has been moved to the bd82x6x bootblock.
For Samsung Stumpy and Lumpy mainboards and the
Intel EmeraldLake2 reference board.
Change-Id: I5ce54f57b8e1dd732c8a5ae71d7511703de91a0e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1307
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
The only difference in this code on all our platforms is the array
describing the GPIOs. Hence, only keep that array in the mainboard
ChromeOS directory and move everything else to generic ChromeOS ACPI
code.
Change-Id: I9fc75842af64530c1255bea1c5f803c5316d6da6
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1278
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Use of uma_resource() in AMD northbridge code created a memory
resource marked as reserved. Such resources are removed
from system memory in write_coreboot_table().
Change-Id: Ib5e49e851d6622d8ece9d6d612e245b3962b9167
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1233
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Remove the menuconfig warning which comes up every time.
src/mainboard/asus/Kconfig:85:warning: multi-line strings not supported
Change-Id: I0ec0a0b625a33edd1d9b250a26aa3e0f42142eca
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1240
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
These boards had identical UMA code:
amd/dbm690t
amd/pistachio
technexion/tim5690
technexion/tim8690
The ones below had whitespace or debug level change
compared to the one above:
kontron/kt690
siemens/sitemp_g1p1
These boards use AMDFAM10 guidelines in code:
asrock/939a785gmh
amd/mahogany
Change-Id: Id7c3f48035727f5847f2d7c3a6e87a3d15582003
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1210
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Following boards had identical code:
advansus/a785e-i
amd/bimini_fam10
amd/mahogany_fam10
asus/m5a88-v
avalue/eax-785e
gigabyte/ma78gm
iei/kino-780am2-fam10
jetway/pa78vm5
Following boards had identical code:
amd/tilapia_fam10
asus/m4a78-em
asus/m4a785-m
gigabyte/ma785gm
gigabyte/ma785gmt
In between the two, only whitespace difference.
Change-Id: Iaa48cc7b0038ebcc81be49219b4fc87670aa9941
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1209
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Following boards had identical code:
amd/inagua
amd/persimmon
The following had only whitespace or debug level changes
compared to ones above.
amd/union_station
amd/south_station
asrock/e350m1
Change-Id: I11ee46e06e1dd510cba551166189ebcaa144464b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1208
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Use of the uma_memory_base and _size variables is very scattered.
Implementation of setup_uma_memory() will appear in each northbridge.
It should be possible to do this setup entirely in northbridge
code and get rid of the globals in a follow-up.
Change-Id: I07ccd98c55a6bcaa8294ad9704b88d7afb341456
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1204
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
And fix the wrong indenting of devicetree.cb while at it.
Change-Id: Idbb19fb5d7155f44675098e79920caf65191c239
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1222
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Linux boots fine :)
Change-Id: Ifda06e5220666534b87f528deae16d8b956c32b3
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/1225
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
All but one board use the default value of enabled. Disabling
this can only increase the number of MTRR registers used.
Change-Id: I7d28adc31b9fae2301e4ff78fcb96486f81d5ec2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1213
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The Kconfig file for this board contains a bogus option called
CORE_GLIU, this change removes it.
Change-Id: I4ea069bdd76be53085ebc9c0fb3dd71ffb2a12e1
Signed-off-by: Ricardo Martins <rasmartins@gmail.com>
Reviewed-on: http://review.coreboot.org/1179
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
used for fan control and thermal management on that board.
Change-Id: I4e5c986ab6174b7a356d682e21732c46181af211
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1167
Tested-by: build bot (Jenkins)
With this change it is possible to define serial number
and version of the mainboard. These informations are used
in SMBIOS tables.
Change-Id: I1634882270f6cb94e00aceb7832e7fd14adc186b
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/1163
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The new broadcast code doesn't support serial init - if a CPU
needs serial init, this should be handled in the model specific CPU
init code.
Change-Id: I7cafb0af10d712366819ad0849f9b93558e9d46a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1140
Tested-by: build bot (Jenkins)
They used MP_IRQ_TRIGGER_LEVEL, but it should be MP_IRQ_TRIGGER_EDGE.
While at it, uses mptable_lintsrc() instead.
Change-Id: Ie71311b8bf865889cf0d8808467df98af4b0132d
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1136
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This adds basic supported for the Supermicro X7DB8. Basic means that
almost all onboard peripherals are working. Known problems are:
- mptable needs to be written dynamically. If you plan to use Add on
cards, modify mptable.c according to your needs. A patch to add generic
mptable autogeneration based on devicetree is coming up.
Change-Id: I5eaac32a8bafa69a05929cf08d869127b9464661
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/493
Tested-by: build bot (Jenkins)
