The value of 0x4 (60 Ohm) apperas to be causing lots of problems.
Since 0x1 (34.3 Ohm) was _almost_ right, let's try 0x2 (40 Ohm) and
hope it's the sweet spot.
BRANCH=None
BUG=chrome-os-partner:43626
TEST=My mickey now boots up
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 06db96e00d39972edbaf8429cbe88bbc66804e15
Original-Change-Id: If8b7d51d058ae000c0af189a648c62fa38a872ac
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291121
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-(cherry picked from commit 0dabadca1ab3bb310f85646d020bdcf672014071)
Original-Reviewed-on: https://chromium-review.googlesource.com/291291
Change-Id: Id32790c894c09616e32503aa790fa294093eca8a
Reviewed-on: http://review.coreboot.org/11386
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This basically does the same thing for firmware what CL:290631
did in the kernel. We want to keep the modem off until it needs
to be used to avoid enumeration/detection issues.
BUG=chrome-os-partner:43271
BRANCH=none
TEST=needs testing
Change-Id: I3b63a77c732dc4895b728b30f1dd71210a9c0e90
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: a90ccd7fbffe44abe05e96341cc77067442c85e4
Original-Change-Id: I3516de1ea9160f7186ad7f5fb3b5d29ac73143b5
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290890
Original-Reviewed-by: Alexandru Stan <amstan@chromium.org>
Reviewed-on: http://review.coreboot.org/11385
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The NV security team requested that coreboot allocate the NVDEC
and TSEC carveouts. Added code to set up NVDEC (1 region, 1MB)
and TSEC (2 regions, splitting 2MB), and set their lock bits.
Kernel/trusted code should be able to use the regions now.
Note that this change sets the UNLOCKED bit in Carveout1Cfg0
and Carveout4Cfg0/5Cfg0 (bit 1) to 0 in the BCT .inc files
(both 3GB and 4GB BCTs) so that the BOMs can be written.
Any future revisions to these BCT files should take this
into account.
BUG=None
BRANCH=None
TEST=Built and booted on my P5 A44. Saw the carveout regions
in the boot spew, and CBMEM living just below the last region
(TSEC). Dumped the MC GeneralizedCarveoutX registers and
verified their values (same as BCT, with only BOM/CFG0 changed).
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: a34b0772cd721193640b322768ce5fcbb4624f23
Original-Change-Id: I2abc872fa1cc4ea669409ffc9f2e66dbbc4efcd0
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/290452
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-(cherry picked from commit f3bbf25397db4d17044e9cfd135ecf73df0ffa60)
Original-Reviewed-on: https://chromium-review.googlesource.com/291081
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Change-Id: I924dfdae7b7c9b877cb1c93fd94f0ef98b728ac5
Reviewed-on: http://review.coreboot.org/11381
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Do not guard the inclusion of "drivers/intel/gma/int15.h"
and "arch/interrupt.h" with configs that control option rom execution.
These headers already have the proper guards. The
install_intel_vga_int15_handler() is unconditionally called, even when
the header that declares it is guarded out.
Change-Id: Ia273437486f5802aa2b53212f2a1b5704c9485fa
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11379
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This seems like more of a debug option, than something that should
be forced to be enabled by the platform. Since it's causing a Kconfig
warning, I'm just removing it.
The alternative to removing it would be to add dependencies on
CONSOLE_CBMEM && !CONSOLE_SERIAL
Change-Id: Ifc4e4cbeea08a503c38827dd75e0e2e78e8a5eda
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11343
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Move all the various places that look at board specific GPIOs into
the mainboard gpio.h so it can be easily ported to new boards.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados p2
Original-Change-Id: I3f1754012158dd5c7d5bbd6e07e40850f21af56d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293942
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I93c4dc1795c1107a3d96e686f03df3199f30de8a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11282
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Implement the required Chrome OS specific handlers to read the
recovery mode, clear the recovery mode, read the lid switch state,
and read the write protect state using the appropriate methods.
Also update the Chrome OS ACPI device to use the GPIO definitions
that are exposed now by the SOC.
BUG=chrome-os-partner:43515
BRANCH=none
TEST=build and boot on glados and successfully enter recovery mode
Original-Change-Id: Ifd51c11dc71b7d091615c29a618454a6a2cc33d7
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293515
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia6ef83a80b9729654bc87bb81bd8d7c1b01d7f42
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11281
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The part number was the same as the H9CCNNNBLTLAR which means it
is not possible to distinguish the two based on part number alone.
This breaks mosys and thus the factory tests.
BUG=chrome-os-partner:43514
BRANCH=none
TEST=boot on glados P2 SKU3 and verify memory reported by mosys
Original-Change-Id: I606ef3989bd7273d134a258bc933088ccc865542
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293513
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I7cea7cc4c61a20fda47673c8e25c431d391aa3bc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11279
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add the ELAN touchscreen device in ACPI to bind it to the I2C
device at bus I2C0, address 0x10, interrupt 31 (GPP_E7).
BUG=chrome-os-partner:43514
BRANCH=none
TEST=boot on glados P2 and see touchscreen initialized by kernel
Original-Change-Id: I23b071b2767547baed239c94216cda6162d045dd
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293512
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I8a9492e6fa1f650cef0871329ae8944caffdaf5a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11278
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Clean up the device code for the glados mainboard, using
the defined values for interrupts by the SOC and moving the
various codec i2c addresses to the top of the file.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados
Original-Change-Id: Iead1aeb54363b15a6176d4f4a9511674195c0505
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293511
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I083c9ef6140e20a433cb2017e4c3cbc7a41e8fed
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11277
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patche enables the deep S5 and disables Deep S3.
Kunimitsu does not resume from deep S3. This change will
unblock the S3 resume path on kunimitsu board.
BRANCH=None
BUG=chrome-os-partner:42331
TEST=Built and booted on kunimitsu; check s3 works.
Original-Change-Id: Ia828a39bceef615fd194bb3614ba2de87c3af805
Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291250
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I07b95a324a27ab658e80674686b47b86412ea097
Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Reviewed-on: http://review.coreboot.org/11274
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Move the CHROMEOS dependent symbols VIRTUAL_DEV_SWITCH and
VBOOT_DYNAMIC_WORK_BUFFER under the CHROMEOS config options for the
mainboards that use them.
Change-Id: Iad126cf045cb3a312319037aff3c4b1f15f6529d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11336
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Add 'select MAINBOARD_HAS_NATIVE_VGA_INIT' which is just used as a gate
symbol to display MAINBOARD_DO_NATIVE_VGA_INIT to the mainboards that
are already selecting MAINBOARD_DO_NATIVE_VGA_INIT.
Since MAINBOARD_HAS_NATIVE_VGA_INIT is not used in any code, this should
not have any other effects.
This fixes the warning:
warning: (BOARD_SPECIFIC_OPTIONS) selects MAINBOARD_DO_NATIVE_VGA_INIT
which has unmet direct dependencies (VENDOR_ASUS && BOARD_ASUS_KFSN4_DRE
|| MAINBOARD_HAS_NATIVE_VGA_INIT)
Change-Id: I8ceee69ebae90dc32f55df58c2e80fe25397f049
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11301
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The AMD K8 northbridge uses the Kconfig symbol QRANK_DIMM_SUPPORT,
but the symbol was used on a number of Family 10 boards as well.
AMD Family 10 doesn't use this Kconfig symbol for anything.
I verified that the symbol wasn't used actually getting used in any
of these platforms.
Fixes Kconfig warnings for these 19 mainboards:
warning: (BOARD_SPECIFIC_OPTIONS...) selects QRANK_DIMM_SUPPORT which
has unmet direct dependencies (NORTHBRIDGE_AMD_AMDK8)
Change-Id: I454992a4975566fd6439a21f5a800d0cfa1b4d3b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11300
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Add CHROMEOS dependencies to selects for the following Kconfig
symbols:
CHROMEOS_RAMOOPS_DYNAMIC
CHROMEOS_RAMOOPS_NON_ACPI
CHROMEOS_VBNV_CMOS
CHROMEOS_VBNV_EC
CHROMEOS_VBNV_FLASH
EC_SOFTWARE_SYNC
LID_SWITCH
RETURN_FROM_VERSTAGE
SEPARATE_VERSTAGE
VBOOT_DISABLE_DEV_ON_RECOVERY
VBOOT_EC_SLOW_UPDATE
VBOOT_OPROM_MATTERS
VBOOT_STARTS_IN_BOOTBLOCK
WIPEOUT_SUPPORTED
This gets rid of these sorts of Kconfig errors:
warning: BOARD_SPECIFIC_OPTIONS selects CHROMEOS_VBNV_EC which has
unmet direct dependencies (MAINBOARD_HAS_CHROMEOS && CHROMEOS)
Note: These two boards would never actually have CHROMEOS enabled:
intel/emeraldlake2 has MAINBOARD_HAS_CHROMEOS commented out
google/peach_pit doesn't have MAINBOARD_HAS_CHROMEOS
Change-Id: I51b4ee326f082c6a656a813ee5772e9c34f5c343
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11272
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
CHROMEOS is a user-visible bool. It must not be 'select'ed in Kconfig.
That's why we have MAINBOARD_HAS_CHROMEOS. This is the fifth time I
find this being used wrong.
Why is this confusing/so hard to get right?
Change-Id: Icb4629355c63508f5a044b46842524b3d203c2da
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11290
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
(1) Wifi is connected on RP1 which is 1c.0 , so enabling
1c.0 and disabling 1d.0
(2) kepler is on RP5 which is 1c.4, so enabling it
(3) enabling ClkReqSupport for RP1 and RP5 so that L1 substates can
get enabled.
BRANCH=None
BUG=chrome-os-partner:43738
TEST=Built and boot for Kunimitsu. checked all PCIe powersaving
states (LTR, L1, L1S) are enabled
Original-Change-Id: I525661399d1a4d939b53d5ed5f7991598b84ddcd
Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/293482
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ib9a771a6ec137217668fb0385efc13b1824772b4
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: http://review.coreboot.org/11237
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The skylake SoC code now has macros for the previously
hard-code numbers for IRQs and GPEs. Switch over to using
those as they bring a little more clarity.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: Ic8fcc59d680cdddec9dfbc3bf679731f6d786793
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293411
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I594907005372100a3c9d17dda9d17769844ad272
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11234
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Broadwell and Skylake chipsets, along with a few mainboards were
selecting ALWAYS_LOAD_OPROM without making sure that the dependency
for that symbol was met as well.
Looking at the dependencies for VGA_RUN_ROM, we see:
PCI && !PAYLOAD_SEABIOS && !MAINBOARD_DO_NATIVE_VGA_INIT
Since ARCH_X86 selects PCI, that's always met here.
Since Broadwell and Skylake don't have native VGA init yet, that's
not needed.
- Make sure that VGA_RUN_ROM is selected as well.
- Add dependency on !PAYLOAD_SEABIOS for both ALWAYS_LOAD_OPROM and
VGA_RUN_ROM symbols where they're selected.
Fixes Kconfig warning for these boards and chipsets:
warning: (BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS &&
BOARD_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS)
selects ALWAYS_LOAD_OPROM which has unmet direct dependencies
(VGA_ROM_RUN)
Change-Id: I787a87e9467e1fc7afe8b04864b2a89b54824b9f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11246
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order for the EC_SCI_L to work the GPE0 route needs
to be set along w/ the GPE event for the EC. As the GPE0
route is dynamic the EC_SCI_GPI needs to be set along
with the route so everything lines up. In this case, the
GPE0 route is set to the defaults such that GPP_C, GPP_D,
and GPP_E are routed to GPE0 block 0, 1, and 2, respectively.
This works out for glados because the EC_SCI_L is connected
to GPP_E16.
BUG=chrome-os-partner:43778
BRANCH=None
TEST=Built and booted glados. The 'acpi' interrupt in /proc/interrupts
is incrementing as well as /sys/firmware/acpi/interrupts/gpe50.
Original-Change-Id: I71fc4bec124f3ac87453a099412154e67aba6280
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/292011
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Idbb6d29364655537abc9ae6f012b3abb38edf138
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11210
Tested-by: build bot (Jenkins)
Set the EC_SMI_GPI define to be GPP_E15 and route that
GPIO for SMI generation. Also, the mainboard_smi_gpi_handler()
was introduced on skylake in order to process any GPI that could
generate an SMI. Switch to this handler so one can process the
appropriate events.
BUG=chrome-os-partner:43778
BRANCH=None
TEST=Used 'lidclose' on EC command line during depthcharge
to confirm EC_SMI_L generates SMI and shutdown happens.
Original-Change-Id: Ia365b86161670a809e3fa99dde38fccc612d5e77
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291934
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ic16ea8e8d6ff564977ed2081d2353c82af71adea
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11209
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The ec_smi_gpio and alt_gp_smi_en devicetree options are
goign to be removed. The plan for skylake is to set the
settings by the mainboard through either gpio pad
configuration or through helper functions.
Moreover, these values only allow *1* SMI GPIO configuration
in that the following has to be true:
alt_gp_smi_en = 1 << (ec_smi_gpio % 24)
If not, then another gpio(s) from the same group has the
SMI_EN bit set for it.
Lastly, remove all the subsequent dependencies as they are
no longer used: enable_alt_smi() and gpio_enable_group().
BUG=chrome-os-partner:43778
BRANCH=None
TEST=None
Original-Change-Id: I749a499c810d83de522a2ccce1dd9efb0ad2e20a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291931
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I2e1cd6879b76923157268a1449c617ef2aada9c4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11204
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The skylake code is using IED_REGION_SIZE instead of
devicetree.cb. Drop the the option from the device trees.
BUG=chrome-os-partner:43636
BRANCH=None
TEST=None
Original-Change-Id: Ib252266060fbc6ed0eeaac19a6b79c173c6c9a13
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290932
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Trybot-Ready: David James <davidjames@chromium.org>
Change-Id: Ib08628e163ac27d4c49eddcbec6cab3252abd4aa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11200
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In order to run with the debug FSP the SMBus device needs
to be enabled. Additionally, the TCO block lives within
the SMBus device so if TCO is to be employed then the
SMBus device needs to be enabled as a prerequisite.
BUG=chrome-os-partner:42407
BRANCH=None
TEST=Buit and booted into kernel.
Original-Change-Id: I269650fa5222b4741ef495188dff1f4b8176fe89
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290364
Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>
Change-Id: Ia1f72ea7bd70728de83cdff07df9810a326266c2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11181
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Instead of relying on FSP to do gpio configuration in one
place use the native support in coreboot. This also removes
the open coded configuration of the memory configuration
ids.
BUG=chrome-os-partner:42982
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I4655221d821d91a2270d774305a02d6bd5c3959c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289800
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I2e66242d050c3825f6bc65d3d2c7f51d2cdfbd73
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11175
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Enable the Deep Sx pins to allow wake from the EC via LAN_WAKE#.
Report the EC wake pin LAN_WAKE as GPE[112].
BUG=chrome-os-partner:43079
BRANCH=none
TEST=suspend/resume on glados with wake from keyboard
Original-Change-Id: I99664e1e406d15e7460046a6168cbd3a377aaca4
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/288921
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I19db144ed5db183f47af03340886a5e770af8bc8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11171
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I4afec92c57c6af4c99858afae53fa7746f47bc7a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11159
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Derived from what the vendor BIOS is doing.
Change-Id: Ie2cba7b86b6bb3f1dcc4a5e1c189aa45d0aab109
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Found-by: fwts 15.08
Reviewed-on: http://review.coreboot.org/11142
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This adapts Ia5101d5a1 for the p470.
Change-Id: Ib09a0bc58fddd6240834cc890f00df91a74f4161
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11160
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The used functions require the ELOG_GSMI feature, not just ELOG.
Change-Id: If38cf0b710d9236012bfb1f0b119c10f9e533a25
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/11098
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This enables adding the GPU specific entries to the SSDT.
Change-Id: I04d0eb7bf6f3e28d89c9318b777875e8a78b1ab5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11140
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Spike support: QEMU RISCV is broken, and the maintainers at Berkeley
are working on it, but at the moment spike is the only way to test
on riscv. Add support for spike console output for debugging.
Privileged ISA: Update to privileged ISA in RISCV (machine,
supervisor, hypervisor, user modes) broke exisitng RISCV asm, and
bootblock.S was updated to match the new spec. Clean old assembly
[pg: things build with gcc 4.9 now, but don't expect them to work.
Hardcoding register names into the assembler language may not be the smartest
idea of the RISCV folks.]
Change-Id: Ie2c109d3c26712c207512f74f28ce1a925e6e181
Signed-off-by: Thaminda Edirisooriya <thaminda@google.com>
Reviewed-on: http://review.coreboot.org/11078
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some FSF addresses found their way back into our tree.
Change-Id: I34b465fc78734d818eca1d6962a1e62bf9d6e7f3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11145
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
vboot2 requires it
Change-Id: I63bc3f176af72da8ea172a09aa536a10f1184b14
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/11099
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch resolves the outstanding issues with
PCI device enumeration and getting the board to boot into
GNU/Linux with VGA rom.
Previously the board would not boot to GNU/Linux with video,
even if VGA rom was used.
Bugs in the devicetree were fixed according to superiotool output.
Tested on GA-B75M-D3H with VGA rom.
Booted to GNU/Linux (Fedora 22 4.0.4-301.fc22.x86_64)
Change-Id: Ide1f406652659e6f99ee5d993719c187650fffe4
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/10895
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
1. Use enable_imc_thermal_zone to enable fan control.
2. The ACPI method ITZE works on Ubuntu 14.04 and Windows 7
but does not work on Windows 8, so I didn't use it.
After this issue is fixed, I'll add ACPI_ENABLE_THERMAL_ZONE
in bettong/Kconfig.
3. Fan control works on Bettong. I used "APU Validation Toolkit"
to test on Windows 8. This tool can put load to APU. The fan's
behaviour is just like bettong/fchec.c defined. When the temperature
is 40 Celsius, the fan start to run.
Change-Id: I0fc22974a7a7cf3f6bdf5f1c66be95219a177e12
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10721
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Remove the items that are obviously broadwell left or become no-need
with fsp.
BUG=chrome-os-partner:43186
BRANCH=None
TEST=build and boot on sklrvp3.
Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Change-Id: I5dfd62363eecc514e45a7b7ba0961ec7fe0499ee
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 570920cdc9e9c08ee85dcb08998069f1cae2d3cd
Original-Change-Id: I63176584042516c4d28f1bb6403e7bbe5de61010
Original-Reviewed-on: https://chromium-review.googlesource.com/288833
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Robbie Zhang <robbie.zhang@intel.com>
Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-on: http://review.coreboot.org/11072
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Copied from Change-Id: I8d8dc0c0b98bbd194095d47047c8c5199ce17769
BUG=chrome-os-partner:43022
BRANCH=None
TEST=Used physical recovery button to enter dev mode on rialto
Change-Id: I39fd13fee3b9f272f3dc08a447091e05a3d74741
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: eed0652f84cba963044908bb91aac7b8c1c81fd4
Original-Signed-off-by: Jonathan Dixon <joth@chromium.org>
Original-Change-Id: I388d8bb0faa93b54540be095e68450192592a093
Original-Reviewed-on: https://chromium-review.googlesource.com/287660
Original-Reviewed-by: Jason Simmons <jsimmons@chromium.org>
Reviewed-on: http://review.coreboot.org/11069
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Modify MR3_I/O Configuration, Change 34.3 ohms to 60 ohms. This
resolves an issue that was observed on some Mickey boards with
the Samsung 2GB LPDDR3 and is believed to be caused by inferior
routing on the small PCB. (Elpida 2GB LPDDR3 seems unaffected.)
BUG=chrome-os-partner:41905
TEST=Boot from mickey
BRANCH=None
Change-Id: Ic20d9eceb00658c214fd032a2f213dbe0d51a91b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1305010aee6818910ad1dec26d9d948505ca281e
Original-Change-Id: I5517e07fc5716ed4cd58e5502f13ccd61ffb5357
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/286333
Reviewed-on: http://review.coreboot.org/11051
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The PLLU and UTMIPLL power-up sequences have been fixed in the
kernel. It's no longer necessary for the XUSB partitions to
be ungated at boot.
This reverts commit 3a4a8a97c1851b6f3dd211451d9678358fac3ad7.
BUG=chrome-os-partner:41244
TEST=Build and boot on Smaug; xHCI still works.
BRANCH=none
CQ-DEPEND=CL:282765
Change-Id: Id9a1c9960b6c7286b3185c60371d864874f50bb3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d52e50240bca62997af729722fbcdf5226438b7f
Original-Change-Id: Ieb9c8644a5fb108d77703933fde82d359f403fd1
Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/286810
Original-Reviewed-by: Benson Leung <bleung@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Mark Kuo <mkuo@nvidia.com>
Original-Reviewed-by: Mark Kuo <mkuo@nvidia.com>
Reviewed-on: http://review.coreboot.org/11050
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
