coreboot-kgpe-d16/src/soc/intel/tigerlake
Subrata Banik ad08265740 soc/intel/tigerlake: Select SF_MASK_2WAYS_PER_BIT if eNEM is enable
As per TGL EDS doc:575681, two ways will be controlled with one bit
of SF QoS register(SF Mask#1/#2) hence, selects SF_MASK_2WAYS_PER_BIT
for TGL SoC.

Change-Id: Ibeef653e0c510b62880b10b3f9767664d89c9623
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-15 07:12:41 +00:00
..
acpi soc/intel/tigerlake: Enable support for common IRQ block 2021-06-29 21:54:17 +00:00
bootblock Move post_codes.h to commonlib/console/ 2021-08-04 15:15:51 +00:00
include/soc soc/intel/common: Move PMC EPOC related code to Intel common code 2021-06-30 07:34:44 +00:00
romstage soc/intel/tigerlake: Make use of `cpu/intel/cpu_ids.h' 2021-07-17 09:50:32 +00:00
spd util: Add DDR4 generic SPD for MT40A512M16TB-062E:R 2021-06-14 05:27:39 +00:00
acpi.c soc/intel: Drop casts around soc_read_pmc_base() 2021-06-28 04:16:48 +00:00
chip.c soc/intel/tigerlake: Enable support for common IRQ block 2021-06-29 21:54:17 +00:00
chip.h soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OC 2021-05-14 23:00:01 +00:00
chipset.cb soc/intel/tigerlake: Remove obsolete CNVi Bluetooth PCI device 2021-03-15 06:27:15 +00:00
cpu.c soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT 2021-05-07 06:05:37 +00:00
crashlog_lib.c soc/intel/tigerlake: Re-use existing define in CrashLog implementation 2021-03-03 09:02:16 +00:00
dptf.c dptf: Move platform-specific information to struct dptf_platform_info 2021-04-13 08:22:49 +00:00
elog.c soc/intel/*: Update data types for variables holding PCH_DEVFN_* macros 2021-05-03 16:28:53 +00:00
espi.c src: Match array format in function declarations and definitions 2021-05-13 18:34:38 +00:00
finalize.c Move post_codes.h to commonlib/console/ 2021-08-04 15:15:51 +00:00
fsp_params.c soc/intel/tigerlake: Clean up FSP chipset lockdown configuration 2021-08-12 21:42:01 +00:00
gpio.c soc/intel/tigerlake: Add known CPU Port IDs for GPIO communities 2021-05-06 04:12:41 +00:00
gspi.c
i2c.c
Kconfig soc/intel/tigerlake: Select SF_MASK_2WAYS_PER_BIT if eNEM is enable 2021-08-15 07:12:41 +00:00
lockdown.c
Makefile.inc soc/intel/tgl: Hook up ucode for TGL-U and TGL-R 2021-08-13 18:07:22 +00:00
me.c
meminit.c soc/intel/tigerlake: Hook up FSP repository 2021-06-10 05:34:52 +00:00
p2sb.c
pmc.c soc/intel/common: Move PMC EPOC related code to Intel common code 2021-06-30 07:34:44 +00:00
pmutil.c soc/intel/*/pmutil.c: Align cosmetics across platforms 2021-02-24 11:34:42 +00:00
reset.c
smihandler.c soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster 2021-05-07 06:05:18 +00:00
soundwire.c soc/intel/common: Move PMC EPOC related code to Intel common code 2021-06-30 07:34:44 +00:00
spi.c src/soc/intel/tigerlake: Add SPI DMI Destination ID 2020-12-08 22:57:45 +00:00
systemagent.c soc/intel: Replace SA_PCIEX_LENGTH Kconfig options 2021-01-30 23:14:08 +00:00
uart.c soc/intel/*: drop UART pad configuration from common code 2021-03-12 08:48:03 +00:00
xhci.c soc/intel/common: Adapt XHCI elog driver for reuse 2020-12-10 17:45:47 +00:00