coreboot-kgpe-d16/src/soc/intel
Patrick Rudolph 09a106907e soc/intel/cannonlake/bootblock: Fix FSP CAR
Fix FSP CAR on platforms that have ROM_SIZE of 32MiB.
CodeRegionSize must be smaller than or equal to 16MiB
to not overlap with LAPIC or the CAR area at 0xfef00000.

Tested on Intel CFL, the new code allows to boot using FSP-T.

Change-Id: I4dfee230c3cc883fad0cb92977c8f5570e1a927c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01 06:48:44 +00:00
..
apollolake src: Remove unused 'include <cpu/x86/cache.h>' 2020-05-01 06:10:49 +00:00
baytrail src: Remove unused 'include <cpu/x86/cache.h>' 2020-05-01 06:10:49 +00:00
braswell src: Remove not used 'include <smbios.h>' 2020-05-01 06:16:33 +00:00
broadwell src: Remove unused 'include <cpu/x86/cache.h>' 2020-05-01 06:10:49 +00:00
cannonlake soc/intel/cannonlake/bootblock: Fix FSP CAR 2020-05-01 06:48:44 +00:00
common src: Remove unused 'include <cpu/x86/cache.h>' 2020-05-01 06:10:49 +00:00
denverton_ns src: Remove unused 'include <cpu/x86/cache.h>' 2020-05-01 06:10:49 +00:00
icelake src: Remove unused 'include <cpu/x86/cache.h>' 2020-05-01 06:10:49 +00:00
jasperlake soc/intel/jasperlake: Fill PcieRpClkReqDetect from devicetree 2020-05-01 06:17:21 +00:00
quark src: Remove unused 'include <cpu/x86/cache.h>' 2020-05-01 06:10:49 +00:00
skylake src: Remove not used 'include <smbios.h>' 2020-05-01 06:16:33 +00:00
tigerlake soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetree 2020-05-01 06:27:32 +00:00
xeon_sp device: Constify struct device * parameter to acpi_inject_dsdt 2020-04-28 19:51:25 +00:00
Kconfig fsp2_0: Gather Kconfig declarations 2020-04-05 23:26:24 +00:00