Subrata Banik 0e2510f616 soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ... Alder Lake onwards IA SoC to select CAR_HAS_L3_PROTECTED_WAYS from SoC Kconfig and here is modified flow as below: Add new MSR 0xc85 IA32_L3_PROTECTED_WAYS Update eNEM init flow: - Set MSR 0xC85 L3_Protected_ways = (1 << data ways) - 1 Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000 BUG=b:168820083 TEST=Verified filling up the entire cache with memcpy at the beginning itself and then running the entire bootblock, verstage, debug FSP-M without running into any issue. This proves that code caching and eviction is working as expected in eNEM mode. Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>		2021-08-16 05:07:12 +00:00
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bist.h
cache.h
cr.h	arch/x86: Use ENV_X86_64 instead of _x86_64_	2021-07-06 06:09:13 +00:00
gdt.h
lapic.h	cpu/x86/lapic: Drop read/write_around aliases	2021-06-10 20:57:41 +00:00
lapic_def.h	cpu/x86/lapic: Replace LOCAL_APIC_ADDR references	2021-06-11 07:11:43 +00:00
legacy_save_state.h
mp.h	src/cpu/x86: Add helper mp_run_on_all_aps	2021-03-11 15:53:58 +00:00
msr.h	soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig	2021-08-16 05:07:12 +00:00
mtrr.h	cpu/x86/mtrr.h: Rename CORE2 alternative SMRR registers	2020-11-10 06:18:05 +00:00
name.h
pae.h
post_code.h	Move post_codes.h to commonlib/console/	2021-08-04 15:15:51 +00:00
save_state.h	cpu/x86/smm: Add a common save state handling	2020-11-09 10:20:07 +00:00
smi_deprecated.h
smm.h	soc/intel/common/block/smm: Add mainboard_smi_finalize	2021-06-19 00:06:41 +00:00
tsc.h