coreboot-kgpe-d16/src/cpu/intel
Angel Pons 1caa279325 cpu/intel/haswell: Do not include useless µcode updates
There are two types of Haswell/Broadwell platforms: Trad(itional) with
separate CPU and PCH packages, and ULT/ULX where the CPU and PCH share
one package. Mainboards can specify which platform type they are using
the `INTEL_LYNXPOINT_LP` Kconfig option. There are so many differences
between Trad and ULT/ULX that it's not worth doing runtime detection.

The CPUIDs are different for Trad and ULT/ULX platforms, and so are the
µcode updates. So, including Trad µcode updates in a coreboot image for
an ULT/ULX mainboard makes no sense, and vice versa.

Adapt the Makefile so that only relevant µcode updates are added. Also,
add a few comments to indicate which updates correspond to which CPUs.

TEST=Run binwalk on coreboot.rom to verify included µcode updates for:
     - Asrock B85M Pro4 (Haswell Trad)
     - HP Folio 9480M (Haswell ULT/ULX)
     - Purism Librem BDW (Broadwell ULT/ULX)

Change-Id: I6dc9e94ce9fede15cbcbe6be577c48c197a9212a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-09-20 07:51:20 +00:00
..
car arch/x86: Mark prepare_and_run_postcar noreturn 2022-07-14 23:10:30 +00:00
common cpu/intel/common: Add support for energy performance preference (EPP) 2022-03-09 22:57:04 +00:00
fit cbfs: Add CBFS_TYPE_INTEL_FIT and exclude it from CBFS verification 2022-06-01 19:45:22 +00:00
haswell cpu/intel/haswell: Do not include useless µcode updates 2022-09-20 07:51:20 +00:00
hyperthreading
microcode cpu: Get rid of unnecessary blank line {before,after} barce 2022-07-17 18:57:54 +00:00
model_6bx cpu/x86/lapic: Move LAPIC configuration to MP init 2022-02-05 07:59:04 +00:00
model_6ex cpu/x86/lapic: Move LAPIC configuration to MP init 2022-02-05 07:59:04 +00:00
model_6fx cpu: Get rid of unnecessary blank line {before,after} barce 2022-07-17 18:57:54 +00:00
model_6xx cpu/x86/lapic: Move LAPIC configuration to MP init 2022-02-05 07:59:04 +00:00
model_65x cpu/x86/lapic: Move LAPIC configuration to MP init 2022-02-05 07:59:04 +00:00
model_67x cpu/x86/lapic: Move LAPIC configuration to MP init 2022-02-05 07:59:04 +00:00
model_68x cpu/x86/lapic: Move LAPIC configuration to MP init 2022-02-05 07:59:04 +00:00
model_106cx cpu/x86/lapic: Move LAPIC configuration to MP init 2022-02-05 07:59:04 +00:00
model_206ax cpu: Get rid of unnecessary blank line {before,after} barce 2022-07-17 18:57:54 +00:00
model_1067x cpu/x86/lapic: Move LAPIC configuration to MP init 2022-02-05 07:59:04 +00:00
model_2065x cpu: Get rid of unnecessary blank line {before,after} barce 2022-07-17 18:57:54 +00:00
model_f2x cpu/intel/model_fxx: Select SSE2 2022-06-02 15:58:34 +00:00
model_f3x cpu/intel/model_fxx: Select SSE2 2022-06-02 15:58:34 +00:00
model_f4x cpu/intel/model_fxx: Select SSE2 2022-06-02 15:58:34 +00:00
slot_1 cpu: Get rid of unnecessary blank line {before,after} barce 2022-07-17 18:57:54 +00:00
smm
socket_441
socket_BGA956
socket_FCBGA559 nb/intel/pineview: Use cbfs mcache 2022-04-27 13:04:12 +00:00
socket_LGA775
socket_m cpu/intel/socket_m: Drop 'select SSE' 2022-01-27 14:51:24 +00:00
socket_mPGA604
socket_p cpu/intel/socket_p: Increase DCACHE_RAM_SIZE 2022-04-27 13:04:23 +00:00
speedstep
turbo
Kconfig
Makefile.inc