Mike Banon 1e6a227f10 nb/amd/agesa/family15tn: define macros for GNB and IOMMU devices ... Follow the example of newer AMD code for Stoneyridge and Picasso. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I9c17d4cb4953b28a47483f5d7db308ccc89e9281 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>		2020-11-23 19:18:03 +00:00
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acpi	ACPI: Define acpi_get_preferred_pm_profile()	2020-11-19 22:58:41 +00:00
arch	cpu/intel/common: Fill cpu voltage in SMBIOS tables	2020-11-22 22:31:40 +00:00
commonlib	cbfs: Add metadata cache	2020-11-21 10:43:53 +00:00
console	console: Override uart base address	2020-11-09 07:46:10 +00:00
cpu	cpu/intel/common: Fill cpu voltage in SMBIOS tables	2020-11-22 22:31:40 +00:00
device	device/pci: Add NULL check for PCI driver's .ops	2020-11-16 12:15:38 +00:00
drivers	drivers/tpm: Move PPI stub	2020-11-22 22:27:29 +00:00
ec	ec/google/chromeec: Add more wrappers for regulator control	2020-11-18 06:13:12 +00:00
include	cpu/intel/common: Fill cpu voltage in SMBIOS tables	2020-11-22 22:31:40 +00:00
lib	cbfs: Add metadata cache	2020-11-21 10:43:53 +00:00
mainboard	mb/google/zork: correct USB2 phy TXVREFTUNE0 parameter name	2020-11-23 16:44:59 +00:00
northbridge	nb/amd/agesa/family15tn: define macros for GNB and IOMMU devices	2020-11-23 19:18:03 +00:00
security	cbfs: Add metadata cache	2020-11-21 10:43:53 +00:00
soc	mb/google/zork: correct USB2 phy TXVREFTUNE0 parameter name	2020-11-23 16:44:59 +00:00
southbridge	sb/intel/lynxpoint: Drop invalid SATA registers	2020-11-23 13:00:14 +00:00
superio	superio/smsc/sio1036: Support 16-bit IO port addressing	2020-11-18 13:12:11 +00:00
vendorcode	vendorcode/eltan/security: Add dependency for menu items	2020-11-22 22:27:43 +00:00
Kconfig	soc/intel/xeon_sp: Move function debug macros	2020-10-29 16:44:19 +00:00