Yidi Lin 2751d2922f Use common GCD function ... Change-Id: I30e4b02a9ca6a15c9bc4edcf4143ffa13a21a732 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78799 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>		2023-11-04 17:06:42 +00:00
..
amd	soc/amd/mendocino: Conditionally select HAVE_FSP_LOGO_SUPPORT	2023-11-03 21:33:27 +00:00
cavium	soc/cavium/cn81xx/bootblock_custom.S: Specify arch	2023-10-20 14:30:54 +00:00
example/min86	soc: Remove SOC_SPECIFIC_OPTIONS	2023-08-21 23:45:43 +00:00
intel	soc/intel/meteorlake: Consolidate settings for enabling tracehub	2023-11-04 16:56:48 +00:00
mediatek	device/device.h: Rename pci_domain_scan_bus	2023-10-20 14:24:57 +00:00
nvidia	memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere	2023-10-11 12:08:22 +00:00
qualcomm	device/device.h: Rename pci_domain_scan_bus	2023-10-20 14:24:57 +00:00
rockchip	Use common GCD function	2023-11-04 17:06:42 +00:00
samsung	memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere	2023-10-11 12:08:22 +00:00
sifive/fu540	memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere	2023-10-11 12:08:22 +00:00
ti
ucb/riscv