coreboot-kgpe-d16/src
Jacob Garber 27ca962058 nb/amd/amdfam10: die() on out of bounds reads
These two functions try to access arrays of lengths 32 and 64 at indices
of at most 259 and 71 (respectively). Something here is seriously wrong.
This code was introduced in 2007, and aside from cosmetic changes, has
had no modifications since then. I don't know what this code is supposed
to do, and asking around on IRC, no one else did either. Until someone
has the interest and time to work on it, let's at least add a die() to
prevent the out of bounds access and alert the user that something is
wrong.

Change-Id: I5fc15a50a9f0e97add31e3a40da82a15f7427358
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 12296{79-82}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-06-13 20:13:03 +00:00
..
acpi
arch stage_cache: Make empty inline function if CONFIG_NO_STAGE_CACHE enable 2019-06-13 04:39:28 +00:00
commonlib cbmem: Add ID for UCSI 2019-06-07 20:50:39 +00:00
console console: Allow using vprintk() with disabled console 2019-06-11 17:29:02 +00:00
cpu Rampayload: Able to build coreboot without ramstage 2019-06-11 15:49:25 +00:00
device src/device: Prevent attack on null pointer dereference 2019-06-03 13:25:25 +00:00
drivers {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support 2019-06-12 07:47:13 +00:00
ec ec/google/wilco: Add UCSI support 2019-06-07 20:51:16 +00:00
include Set ENV_PAYLOAD_LOADER to ENV_POSTCAR when CONFIG_RAMPAYLOAD is enabled 2019-06-13 04:40:05 +00:00
lib stage_cache: Make empty inline function if CONFIG_NO_STAGE_CACHE enable 2019-06-13 04:39:28 +00:00
mainboard mb/google/{hatch, sarien, arcada}: Make HECI1 chip config disable 2019-06-13 04:39:01 +00:00
northbridge nb/amd/amdfam10: die() on out of bounds reads 2019-06-13 20:13:03 +00:00
security vboot: recovery path should finalize work context 2019-06-12 05:45:10 +00:00
soc soc/intel/{cml, whl}: Add option to skip HECI disable in SMM 2019-06-13 04:38:39 +00:00
southbridge sb/amd/sb700: Fix misleading formatting 2019-06-07 21:30:57 +00:00
superio superio/fintek/f71863fg: Remove variable set but not used 2019-05-25 18:20:15 +00:00
vendorcode vendorcode/intel/fsp/fsp2_0/cometlake: Update FSP-M/S header files as per v1155 2019-06-12 22:48:36 +00:00
Kconfig Rampayload: Able to build coreboot without ramstage 2019-06-11 15:49:25 +00:00