Zhao, Lijian 2b9a5f5688 soc/intel/apollolake: Fix northbridge _crs scope ... Move _CRS scope from MCHC device only to whole pci root bus. Otherwise ACPI will not able to assign resource to devices other than MCHC. Change-Id: Iaa294c63e03a4fc6644f1be5d69ab3de077e6cc3 Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/14477 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2016-04-28 05:14:47 +02:00
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acpi	acpi/: add missing license header	2016-01-14 22:52:11 +01:00
arch	lib: add common write_tables() implementation	2016-04-21 20:49:05 +02:00
commonlib	ensure correct byte ordering for cbfs segment list	2016-04-25 23:30:00 +02:00
console	arch/x86: introduce postcar stage/phase	2016-03-23 14:24:30 +01:00
cpu	cpu/x86/tsc: Compile TSC timer for postcar as well	2016-04-11 17:56:57 +02:00
device	payloads: add iPXE 'payload' build	2016-04-13 17:45:37 +02:00
drivers	drivers/ricoh: Fully switch to src/drivers/[X]/[Y]/ scheme	2016-04-22 20:11:52 +02:00
ec	kbuild: Allow drivers to fit src/drivers/[X]/[Y]/ scheme	2016-04-19 18:34:18 +02:00
include	lib: add common write_tables() implementation	2016-04-21 20:49:05 +02:00
lib	ensure correct byte ordering for cbfs segment list	2016-04-25 23:30:00 +02:00
mainboard	mainboard/amenia: Enable Chrome EC Interface/Keyboard	2016-04-28 05:13:54 +02:00
northbridge	nb/amd/mct_ddr3: Report correct DIMM in MRS setup routines	2016-04-26 16:54:04 +02:00
soc	soc/intel/apollolake: Fix northbridge _crs scope	2016-04-28 05:14:47 +02:00
southbridge	intel/i82801ax: Fix IDE setup console log	2016-04-22 17:25:19 +02:00
superio	superio/smsc/mec1308: Fix AddressMax value for SMBX mailbox	2016-04-13 23:39:28 +02:00
vendorcode	AGESA vendorcode: Fix type mismatch	2016-04-21 07:39:13 +02:00
Kconfig	arch: use Kconfig variable for coreboot table size	2016-04-21 20:40:40 +02:00