Subrata Banik 32e0673232 soc/intel/common/cse: Rework heci_disable function ... This patch provides the possible options for SoC users to choose the applicable interface to make HECI1 function disable at pre-boot. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_SBI` config is used for disabling heci1 using non-posted sideband write (inside SMM) after FSP-S sets the postboot_sai attribute. Applicable from CNL PCH onwards. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PMC_IPC` config is used for disabling heci1 using PMC IPC command `0xA9`. Applicable from TGL PCH onwards. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR` config is used for disabling heci1 using private configuration register (PCR) write. Applicable for SoC platform prior to CNL PCH. Additionally, add PID_CSME0 macro for SKL, Xeon_SP and APL to fix the compilation failure. Finally, rename heci_disable() function to heci1_disable() to make it more meaningful. BUG=none TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7e0bab0004013b999ec1e054310763427d7b9348 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>		2022-02-02 07:09:28 +00:00
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acpi	soc/intel/skylake/acpi: Replace Add(a,b) with ASL 2.0 syntax	2021-12-31 09:00:25 +00:00
bootblock	soc/intel/skylake: move heci_init() from bootblock to romstage	2022-01-27 10:46:53 +00:00
include/soc	soc/intel/common/cse: Rework heci_disable function	2022-02-02 07:09:28 +00:00
nhlt
romstage	soc/intel/skylake: move heci_init() from bootblock to romstage	2022-01-27 10:46:53 +00:00
acpi.c	soc/intel: generate SSDT instead of using GNVS for SGX	2021-11-09 16:02:19 +00:00
chip.c	soc/intel/skl: Replace dt HeciEnabled by HECI1 disable config	2022-01-16 13:33:14 +00:00
chip.h	soc/intel/skl: Replace dt HeciEnabled by HECI1 disable config	2022-01-16 13:33:14 +00:00
chipset.cb
cpu.c	soc/intel/common/cpu: Use SoC overrides to get CPU privilege level	2022-01-19 09:57:47 +00:00
elog.c
fadt.c	soc/intel/skylake: switch to common ACPI code	2021-10-17 17:27:43 +00:00
finalize.c	soc/intel/skl: Replace dt HeciEnabled by HECI1 disable config	2022-01-16 13:33:14 +00:00
gpio.c
graphics.c	soc/intel: Replace bad uses of find_resource	2021-11-04 17:34:30 +00:00
gspi.c
i2c.c
irq.c
Kconfig	soc/intel/common/thermal: Refactor thermal block to improve reusability	2021-11-25 07:18:04 +00:00
lockdown.c
lpc.c	soc/intel/skylake: Drop reg-script usage	2021-09-29 21:22:38 +00:00
Makefile.inc	Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"	2021-11-15 12:00:12 +00:00
me.c
p2sb.c
pmc.c	soc/intel/{skl,cnl,dnv}: disable PM ACPI timer if chosen	2021-10-17 13:58:15 +00:00
pmutil.c
reset.c
sd.c
smihandler.c
spi.c
systemagent.c	Rename ECAM-specific MMCONF Kconfigs	2021-11-10 17:24:16 +00:00
uart.c
vr_config.c	soc/intel/{skylake/cannonlake}: Fix bug in vr_config	2021-12-10 14:30:12 +00:00
xhci.c