4e9bb3308e
Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space. Some platforms have a different way of mapping the PCI config
space to memory. This patch renames the following configs to
make it clear that these configs are ECAM-specific:
- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH
Please refer to CB:57861 "Proposed coreboot Changes" for more
details.
BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
Make sure Jenkins verifies that builds on other boards
Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
25 lines
666 B
Text
25 lines
666 B
Text
config SOC_EXAMPLE_MIN86
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bool
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help
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This example SoC code along with the example/min86 mainboard
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should serve as a minimal example how a buildable x86 SoC code
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base can look like.
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This can serve, for instance, as a basis to add new SoCs to
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coreboot. Starting with a buildable commit should help with
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the review of the actual code, and also avoid any regressions
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when common coreboot code changes.
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if SOC_EXAMPLE_MIN86
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config SOC_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_X86
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select NO_MONOTONIC_TIMER
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select NO_ECAM_MMCONF_SUPPORT
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select UNKNOWN_TSC_RATE
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config DCACHE_BSP_STACK_SIZE # required by arch/x86/car.ld
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default 0x100
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endif
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