Ronak Kanabar 35d7843799 soc/intel/tigerlake: Correct FSP log interface ... select correct UART settings according to Kconfig DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART Add check for DEBUG_INTERFACE_TRACEHUB selection and set "PcdDebugInterfaceFlags" UPD accordingly. BUG=None TEST=boot jslrvp board with Debug FSP and check FSP UART log Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>		2020-03-11 14:38:17 +00:00
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apollolake	intel/soc: skl,apl,cnl,icl,tgl: add INTRUDER relevant registers	2020-03-07 20:32:46 +00:00
baytrail	src: capitalize 'PCIe'	2020-03-04 15:43:30 +00:00
braswell	soc/intel/braswell/chip.h: Include smbios.h for Type9 Entries	2020-03-09 11:03:41 +00:00
broadwell	src: capitalize 'PCIe'	2020-03-04 15:43:30 +00:00
cannonlake	soc/intel: fix eist enabling	2020-03-10 20:29:10 +00:00
common	soc/intel/common/block: tco: enable intruder SMI if selected	2020-03-11 14:28:53 +00:00
denverton_ns	soc/intel/dnv: Set INT_LINE accouting for PIRQ routing & swizzling	2020-03-10 20:45:53 +00:00
icelake	soc/intel: fix eist enabling	2020-03-10 20:29:10 +00:00
quark	soc/intel: Add get_pmbase	2020-02-04 18:54:01 +00:00
skylake	soc/intel: fix eist enabling	2020-03-10 20:29:10 +00:00
tigerlake	soc/intel/tigerlake: Correct FSP log interface	2020-03-11 14:38:17 +00:00
xeon_sp	soc/intel/xeon-sp,mb/ocp/tiogapass: Don't fake binaries	2020-03-10 11:52:45 +00:00
Kconfig	soc/intel: Add Intel Xeon Scalable Processor support	2020-03-06 08:19:59 +00:00