Frank Vibrans 39fca80b00 This code provides cpu northbridge initialization for Family 14h cpus. It is dependent on the AMD Agesa code. ... Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1		2011-02-14 18:35:15 +00:00
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agesa_wrapper	This code provides cpu northbridge initialization for Family 14h cpus. It is dependent on the AMD Agesa code.	2011-02-14 18:35:15 +00:00
amdfam10	Fix some settings fo AMD MCT. It is based on BIOS test suite.	2011-01-06 02:18:12 +00:00
amdht	Convert some comments to proper Doxygen syntax.	2010-10-26 22:46:43 +00:00
amdk8	Implemented workaround for erratum 169, obsoleting erratum 131.	2011-02-10 07:51:51 +00:00
amdmct	For Cx, each ChipSel need to be sent MR command.	2011-01-20 02:09:24 +00:00
gx1	We hardcode highmemory size in every northbridge! This is bad, and especially if suspend to ram is involved. Let the default be taken from cbmem.h which also handles the suspend logic.	2010-12-13 19:50:25 +00:00
gx2	Add a GX2 Kconfig option to choose the framebuffer size.	2011-01-19 07:25:26 +00:00
lx	Use die() to assure the processor can't wake up from an interrupt.	2010-12-30 19:21:08 +00:00
Kconfig	This code provides cpu northbridge initialization for Family 14h cpus. It is dependent on the AMD Agesa code.	2011-02-14 18:35:15 +00:00
Makefile.inc	This code provides cpu northbridge initialization for Family 14h cpus. It is dependent on the AMD Agesa code.	2011-02-14 18:35:15 +00:00