ad62b9af65
GLK has a dedicated USB2 port that is used specifically for CNVi BT. This requires that the ACPI tables define an additional USB 2 port which results in _ADR for USB 3 ports being different for GLK than APL. This change splits the ports in xhci.asl into APL and GLK specific ports.asl and selects the appropriate file based on CONFIG_SOC_INTEL_GLK. It also adds support for returning HS09 for GLK if ACPI name is requested for that port. BUG=b:123670712 BRANCH=octopus TEST=Verified that generated DSDT for octopus (GLK) includes HS09 and for reef (APL) does not include HS09 definition. Change-Id: I2d3d3690ec9ea1f6e35c38c3b3cbb82e961b7950 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31172 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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| .. | ||
| dptf.asl | ||
| globalnvs.asl | ||
| gpio.asl | ||
| gpiolib.asl | ||
| lpc.asl | ||
| lpss.asl | ||
| northbridge.asl | ||
| pch_hda.asl | ||
| pci_irqs.asl | ||
| pcie.asl | ||
| pcie_port.asl | ||
| platform.asl | ||
| pmc_ipc.asl | ||
| scs.asl | ||
| sleepstates.asl | ||
| soc_int.asl | ||
| southbridge.asl | ||
| xhci.asl | ||
| xhci_apl_ports.asl | ||
| xhci_glk_ports.asl | ||