Arthur Heymans 45a6ae35ef soc/intel/xeon_sp/skx: Properly set up MTRR's ... Don't depend on the MTRR setup left over from FSP-M ExitTempRam. Change-Id: I299123b3cd3c37b4345102c20fda77bf261892a2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>		2020-12-21 02:37:13 +00:00
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amd	soc/amd/picasso: move sb_clk_output_48Mhz from acp to fch	2020-12-19 16:29:44 +00:00
cavium	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
example	x86: Add a minimal example SoC along with a board	2020-10-30 21:34:18 +00:00
intel	soc/intel/xeon_sp/skx: Properly set up MTRR's	2020-12-21 02:37:13 +00:00
mediatek	soc/mediatek/mt8192: Do the dramc pinmux selection	2020-12-16 08:03:59 +00:00
nvidia	drivers: Replace set_vbe_mode_info_valid	2020-12-17 06:21:56 +00:00
qualcomm	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
rockchip	drivers: Replace set_vbe_mode_info_valid	2020-12-17 06:21:56 +00:00
samsung	cbfs: Enable CBFS mcache on most chipsets	2020-12-02 22:12:10 +00:00
sifive	cbfs: Enable CBFS mcache on most chipsets	2020-12-02 22:12:10 +00:00
ti	cbfs: Enable CBFS mcache on most chipsets	2020-12-02 22:12:10 +00:00
ucb