Subrata Banik 2ccc0a4d9f soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h ... Lists of changes: 1. Rename MISCCFG_ENABLE_GPIO_PM_CONFIG -> MISCCFG_GPIO_PM_CONFIG_BITS 2. Move MISCCFG_GPIO_PM_CONFIG_BITS definition from intelblock/gpio.h to soc/gpio.h. Refer to detailed description below to understand the motivation behind this change. An advanced GPIO PM capabilities has been introduced since CNP PCH, refer to 'include/intelblock/gpio.h' for detailed GPIO PM bit definitions. Now with TGP PCH, additional bits are defined in the MISCCFG register for GPIO PM control. This results in different SoCs supporting different number of bits. The bits defined in earlier platforms (CNL, CML, ICL) are present on TGL, JSL and ADL too. Hence, refactor the common GPIO code to keep the bit definitions in intelblock/gpio.h, but the definition of MISCCFG_GPIO_PM_CONFIG_BITS is moved to soc/gpio.h so that each SoC can provide this as per hardware support. TEST=On ADL, TGL and JSL platform. Without this CL : GPIO COMM 0 MISCCFG:0xC0 (Bit 6 and 7 enable) With this CL : GPIO COMM 0 MISCCFG: 0x00 (Bit 6 and 7 disable) Change-Id: Ie027cbd7b99b39752941384339a34f8995c10c94 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>		2021-03-27 04:23:12 +00:00
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acpi	soc/intel: Include gfx.asl from northbridge	2021-03-01 08:32:47 +00:00
bootblock	soc/intel: Drop bootblock_cpu_init() function	2021-03-01 19:43:04 +00:00
include/soc	soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h	2021-03-27 04:23:12 +00:00
romstage	soc/intel: Drop romstage_pch_init() function	2021-03-01 19:41:17 +00:00
acpi.c	soc/intel: Factor out identical acpigen GPIO helpers	2021-03-01 19:37:56 +00:00
chip.c	soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h	2021-03-27 04:23:12 +00:00
chip.h	soc/intel: Retype CnviBtAudioOffload devicetree option	2021-03-03 09:02:03 +00:00
cpu.c	src: Remove unused <arch/cpu.h>	2021-02-11 10:25:23 +00:00
elog.c
espi.c
finalize.c
fsp_params.c	soc/intel/elkhartlake: Remove unused <string.h>	2021-02-16 17:30:27 +00:00
gpio.c
gspi.c
i2c.c
Kconfig	soc/intel: Factor out common smmrelocate.c	2021-03-03 09:06:09 +00:00
lockdown.c
Makefile.inc	soc/intel: Factor out common smmrelocate.c	2021-03-03 09:06:09 +00:00
me.c
meminit.c	spd_bin: Replace get_spd_cbfs_rdev() with spd_cbfs_map()	2021-03-17 08:10:35 +00:00
p2sb.c
pmc.c
pmutil.c	soc/intel/*/pmutil.c: Align cosmetics across platforms	2021-02-24 11:34:42 +00:00
reset.c
sd.c
smihandler.c	soc/intel: Remove unused <console/console.h>	2021-02-15 10:50:09 +00:00
spi.c
systemagent.c	soc/intel: Replace SA_PCIEX_LENGTH Kconfig options	2021-01-30 23:14:08 +00:00
uart.c	soc/intel/*: drop UART pad configuration from common code	2021-03-12 08:48:03 +00:00