coreboot-kgpe-d16/src
Furquan Shaikh 581c42807d soc/intel/apollolake: Set default memory type to uncacheable
Set the default memory type in MTRRCap register to 0. This ensures
that even if the MTRR Enable bit is set in MTRRCap register, the
default memory type is still uncacheable.

Change-Id: I63e7993f8b65dabbab60e7c1bb8d6d89ef4da9ee
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14428
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-21 08:24:33 +02:00
..
acpi acpi/: add missing license header 2016-01-14 22:52:11 +01:00
arch bootblock_crt0: Use CR* macros from cpu/x86/cr.h 2016-04-15 01:31:16 +02:00
commonlib arch/x86: introduce postcar stage/phase 2016-03-23 14:24:30 +01:00
console arch/x86: introduce postcar stage/phase 2016-03-23 14:24:30 +01:00
cpu cpu/x86/tsc: Compile TSC timer for postcar as well 2016-04-11 17:56:57 +02:00
device payloads: add iPXE 'payload' build 2016-04-13 17:45:37 +02:00
drivers drivers/ricoh: Switch to src/drivers/[X]/[Y]/ scheme 2016-04-19 18:38:29 +02:00
ec kbuild: Allow drivers to fit src/drivers/[X]/[Y]/ scheme 2016-04-19 18:34:18 +02:00
include kbuild: Allow drivers to fit src/drivers/[X]/[Y]/ scheme 2016-04-19 18:34:18 +02:00
lib program.ld: make sure that zeroptr isn't assigned to debug sections 2016-04-16 01:50:44 +02:00
mainboard mainboard/apple: add license headers 2016-04-21 00:07:45 +02:00
northbridge AMD CIMX: Drop unused code 2016-04-20 15:31:18 +02:00
soc soc/intel/apollolake: Set default memory type to uncacheable 2016-04-21 08:24:33 +02:00
southbridge southbridge/via: Update license headers 2016-04-13 17:36:14 +02:00
superio superio/smsc/mec1308: Fix AddressMax value for SMBX mailbox 2016-04-13 23:39:28 +02:00
vendorcode AGESA vendorcode: Fix type mismatch 2016-04-21 07:39:13 +02:00
Kconfig kbuild: Allow drivers to fit src/drivers/[X]/[Y]/ scheme 2016-04-19 18:34:18 +02:00