coreboot-kgpe-d16/src/soc
Usha P 5e59a82c27 soc/intel/common: Set controller state to active in uart init
Set the controller state to D0 during the uart init sequence, this
ensures the controller is up and active.

One more argument "const struct device *dev" has been added
to uart_lpss_init function.

BUG=b:135941367
TEST=Verify no timeouts seen during UART controller enumeration
     sequence in CML, ICL and APL platforms

Change-Id: Ie91b502a38d1a40a3dea3711b015b7a5b7ede2db
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34810
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21 09:28:46 +00:00
..
amd amd/picasso: Unify SMM relocation 2019-08-16 00:37:31 +00:00
cavium src: Include <stdint.h> instead of <inttypes.h> 2019-08-10 01:33:58 +00:00
imgtec arch/non-x86: Remove use of __PRE_RAM__ 2019-08-20 01:12:28 +00:00
intel soc/intel/common: Set controller state to active in uart init 2019-08-21 09:28:46 +00:00
mediatek mediatek/mt8183: Enlarge PRERAM_CBFS_CACHE region 2019-08-21 09:28:29 +00:00
nvidia arch/non-x86: Remove use of __PRE_RAM__ 2019-08-20 01:12:28 +00:00
qualcomm arch/non-x86: Remove use of __PRE_RAM__ 2019-08-20 01:12:28 +00:00
rockchip src: Include <stdint.h> instead of <inttypes.h> 2019-08-10 01:33:58 +00:00
samsung arch/non-x86: Remove use of __PRE_RAM__ 2019-08-20 01:12:28 +00:00
sifive soc/sifive/fu540: add code for spi and map flash to memory spaces 2019-08-12 08:35:17 +00:00
ucb lib: Rewrite qemu-armv7 ramdetect 2019-07-28 11:31:42 +00:00