5ff742c740
Follow instrcution from https://doc.coreboot.org/acpi/gpio.html to implement GPIO toggling method, covered for both CNP_LP and CNP_H pch. BUG=N/A TEST=Build and boot up fine on sarien platform, add an dummy STSX in DSDT table, read back from iotools to confirm the GPIO tx state get updated. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I006a6a8fc580c73ac0938968397a628a4ffe504f Reviewed-on: https://review.coreboot.org/c/30461 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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apollolake | ||
baytrail | ||
braswell | ||
broadwell | ||
cannonlake | ||
common | ||
denverton_ns | ||
fsp_baytrail | ||
fsp_broadwell_de | ||
icelake | ||
quark | ||
skylake | ||
Kconfig |