Lijian Zhao 6b2c9b1751 mb/google/sarien: Use meaningful SATA mode ... Define SATA mode to AHCI mode instead of 0, make devicetree more readable. BUG=N/A Change-Id: I903545d9487c1409f9008407fe5bee6aa4959b98 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>		2018-12-19 05:30:52 +00:00
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variants	mb/google/sarien: Use meaningful SATA mode	2018-12-19 05:30:52 +00:00
acpi_tables.c
board_info.txt
bootblock.c	mb/google/sarien: Enable Wilco EC	2018-11-02 16:10:07 +00:00
chromeos.c
chromeos.fmd	Revert "google/sarien: Increase BIOS region to 28MB"	2018-12-18 17:51:05 +00:00
dsdt.asl	mb/google/sarien: Enable DPTF	2018-12-04 22:49:25 +00:00
hda_verb.c	mb/google/sarien: Add HD Audio verb table	2018-11-29 12:20:49 +00:00
Kconfig	src/mb/google/*/Kconfig: Consistently use $(...) for variables	2018-12-18 13:25:32 +00:00
Kconfig.name
Makefile.inc	mb/google/sarien: Add HD Audio verb table	2018-11-29 12:20:49 +00:00
ramstage.c	mb/google/sarien: Setup GPIOs again after FSP-S	2018-12-10 08:53:57 +00:00
romstage.c
sku.c	mb/google/sarien: Set SMBIOS mainboard SKU	2018-11-17 07:26:49 +00:00
smihandler.c	mb/google/sarien: Enable Wilco EC	2018-11-02 16:10:07 +00:00