Arthur Heymans 6d3682ee9b soc/amd/genoa: Add minimal viable code for compilation ... This adds a dummy soc (genoa) based on EXAMPLE_MIN86 with amd linker script hooked up. Default to 64bit code as that will be a sensible default for this platform (high memory access required for RAS setup). Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I69253466084d17c4359d7e824d69f12490b076e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76495 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>		2023-09-01 21:07:10 +00:00
..
amd	soc/amd/genoa: Add minimal viable code for compilation	2023-09-01 21:07:10 +00:00
cavium	soc/cavium/cn81xx: Use correct size for MPIDR_EL1 register	2023-05-13 17:22:16 +00:00
example/min86	soc: Remove SOC_SPECIFIC_OPTIONS	2023-08-21 23:45:43 +00:00
intel	soc/intel/cpu: Only show MP PPI option when meaningful	2023-09-01 21:05:27 +00:00
mediatek	soc/mediatek/mt8188: Remove GPT timer init	2023-08-24 12:55:41 +00:00
nvidia	soc/nvidia: Fix incorrect SPDX license	2023-08-24 05:30:10 +00:00
qualcomm	soc/qualcomm: Add missing newlines for logs	2023-08-22 02:28:57 +00:00
rockchip
samsung	soc/samsung/exynos5250/clock: Remove space before semicolon	2023-08-20 22:00:03 +00:00
sifive/fu540	soc/sifive/fu540/Kconfig: Fix opensbi platform	2023-08-04 14:04:13 +00:00
ti
ucb/riscv