6dd7b402d5
This implements dynamic generation of sdcard GpioInt in SSDT. GpioInt in SSDT generation is based on the card detect GPIO if it is provided by the mainboard in devicetree. This implements GNVS variable to store the address of sdcard cd pin. GNVS used to store rxstate of the sdcard cd pin to get card presence. Add _PS0/_PS3 methods to power gate the sd card controller in S0ix and runtime PM. CQ-DEPEND=448173 BUG=chrome-os-partner:63070 TEST=Suspend and resume using 'echo freeze > /sys/power/state'. System should enter S0ix and resume with no issue. Change-Id: Id2c42fc66062f0431385607cff1a83563eaeef87 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/18496 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com> |
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| .. | ||
| cpu.asl | ||
| dptf.asl | ||
| globalnvs.asl | ||
| gpio.asl | ||
| gpiolib.asl | ||
| lpc.asl | ||
| lpss.asl | ||
| northbridge.asl | ||
| pch_hda.asl | ||
| pci_irqs.asl | ||
| pcie.asl | ||
| platform.asl | ||
| pmc_ipc.asl | ||
| scs.asl | ||
| sleepstates.asl | ||
| soc_int.asl | ||
| southbridge.asl | ||
| xhci.asl | ||