coreboot-kgpe-d16/src/include
Simon Glass 7ae73fc3a0 arm64: Use 'payload' format for ATF instead of 'stage'
Switch the BL31 (ARM Trusted Firmware) format to payload so that it can
have multiple independent segments. This also requires disabling the region
check since SRAM is currently faulted by that check.

This has been tested with Rockchip's pending change:

https://chromium-review.googlesource.com/#/c/368592/3

with the patch mentioned on the bug at #13.

BUG=chrome-os-partner:56314
BRANCH=none
TEST=boot on gru and see that BL31 loads and runs. Im not sure if it is
correct though:
CBFS: Locating 'fallback/payload'
CBFS: Found @ offset 1b440 size 15a75
Loading segment from ROM address 0x0000000000100000
  code (compression=1)
  New segment dstaddr 0x18104800 memsize 0x117fbe0 srcaddr 0x100038 filesize 0x15a3d
Loading segment from ROM address 0x000000000010001c
  Entry Point 0x0000000018104800
Loading Segment: addr: 0x0000000018104800 memsz: 0x000000000117fbe0 filesz: 0x0000000000015a3d
lb: [0x0000000000300000, 0x0000000000320558)
Post relocation: addr: 0x0000000018104800 memsz: 0x000000000117fbe0 filesz: 0x0000000000015a3d
using LZMA
[ 0x18104800, 18137d90, 0x192843e0) <- 00100038
Clearing Segment: addr: 0x0000000018137d90 memsz: 0x000000000114c650
dest 0000000018104800, end 00000000192843e0, bouncebuffer ffffffffffffffff
Loaded segments
BS: BS_PAYLOAD_LOAD times (us): entry 0 run 125150 exit 1
Jumping to boot code at 0000000018104800(00000000f7eda000)
CPU0: stack: 00000000ff8ec000 - 00000000ff8f0000, lowest used address 00000000ff8ef3d0, stack used: 3120 bytes
CBFS: 'VBOOT' located CBFS at [402000:44cc00)
CBFS: Locating 'fallback/bl31'
CBFS: Found @ offset 10ec0 size 8d0c
Loading segment from ROM address 0x0000000000100000
  code (compression=1)
  New segment dstaddr 0x10000 memsize 0x40000 srcaddr 0x100054 filesize 0x8192
Loading segment from ROM address 0x000000000010001c
  code (compression=1)
  New segment dstaddr 0xff8d4000 memsize 0x1f50 srcaddr 0x1081e6 filesize 0xb26
Loading segment from ROM address 0x0000000000100038
  Entry Point 0x0000000000010000
Loading Segment: addr: 0x0000000000010000 memsz: 0x0000000000040000 filesz: 0x0000000000008192
lb: [0x0000000000300000, 0x0000000000320558)
Post relocation: addr: 0x0000000000010000 memsz: 0x0000000000040000 filesz: 0x0000000000008192
using LZMA
[ 0x00010000, 00035708, 0x00050000) <- 00100054
Clearing Segment: addr: 0x0000000000035708 memsz: 0x000000000001a8f8
dest 0000000000010000, end 0000000000050000, bouncebuffer ffffffffffffffff
Loading Segment: addr: 0x00000000ff8d4000 memsz: 0x0000000000001f50 filesz: 0x0000000000000b26
lb: [0x0000000000300000, 0x0000000000320558)
Post relocation: addr: 0x00000000ff8d4000 memsz: 0x0000000000001f50 filesz: 0x0000000000000b26
using LZMA
[ 0xff8d4000, ff8d5f50, 0xff8d5f50) <- 001081e6
dest 00000000ff8d4000, end 00000000ff8d5f50, bouncebuffer ffffffffffffffff
Loaded segments
INFO:    plat_rockchip_pmusram_prepare pmu: code d2bfe625,d2bfe625,80
INFO:    plat_rockchip_pmusram_prepare pmu: code 0xff8d4000,0x50000,3364
INFO:    plat_rockchip_pmusram_prepare: data 0xff8d4d28,0xff8d4d24,4648
NOTICE:  BL31: v1.2(debug):
NOTICE:  BL31: Built : Sun Sep  4 22:36:16 UTC 2016
INFO:    GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3
INFO:    plat_rockchip_pmu_init(1189): pd status 3e
INFO:    BL31: Initializing runtime services
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0x18104800
INFO:    SPSR = 0x8

Change-Id: Ie2484d122a603f1c7b7082a1de3f240aa6e6d540
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8c1d75bff6e810a39776048ad9049ec0a9c5d94e
Original-Change-Id: I2d60e5762f8377e43835558f76a3928156acb26c
Original-Signed-off-by: Simon Glass <sjg@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/376849
Original-Commit-Ready: Simon Glass <sjg@google.com>
Original-Tested-by: Simon Glass <sjg@google.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16706
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-06 21:49:52 +02:00
..
boot lib: add common write_tables() implementation 2016-04-21 20:49:05 +02:00
console arch/x86,lib: make cbmem console work in postcar stage 2016-09-19 17:02:17 +02:00
cpu cpu/amd/model_fxx: transition away from device_t 2016-10-01 17:39:05 +02:00
device device/pci.h: change #ifdef argument to __SIMPLE_DEVICE__ 2016-09-04 05:49:15 +02:00
pc80 src/include: Add space around operators 2016-09-20 17:38:56 +02:00
smp src/include: Improve code formatting 2016-09-05 12:28:32 +02:00
superio
sys
tpm_lite tpm2: implement locking firmware rollback counter 2016-07-14 00:00:14 +02:00
antirollback.h vboot2: tpm2 factory initialization. 2016-07-12 00:27:27 +02:00
assert.h
b64_decode.h
base3.h
bcd.h
boardid.h
boot_device.h lib/boot_device: add RW boot device construct 2016-08-19 03:07:05 +02:00
bootblock_common.h bootblock: Declare common bootblock_pre_c_entry routine 2016-06-12 14:52:17 +02:00
bootmem.h lib/bootmem: allow architecture specific bootmem ranges 2016-04-21 20:46:45 +02:00
bootmode.h bootmode: Get rid of CONFIG_BOOTMODE_STRAPS 2016-07-28 00:36:22 +02:00
bootstate.h lib: Add Kconfig to toggle boot state debugging 2016-02-18 00:01:14 +01:00
cbfs.h cbfs: Add "struct" file type and associated helpers 2016-08-27 01:16:22 +02:00
cbmem.h arch/x86,lib: make cbmem console work in postcar stage 2016-09-19 17:02:17 +02:00
delay.h
edid.h edid: Fix a function signature 2016-09-08 23:19:06 +02:00
elog.h drivers/elog: provide return status for all operations 2016-08-09 19:53:21 +02:00
endian.h
fallback.h
fmap.h lib/fmap: provide RW region device support 2016-08-19 18:17:04 +02:00
gic.h src/include: Capitalize CPU, RAM and ROM 2016-07-31 18:30:16 +02:00
gpio.h lib/gpio: add pullup & pulldown gpio_base2_value() variants 2016-07-07 20:44:36 +02:00
halt.h lib: add poweroff() declaration 2016-07-15 08:35:15 +02:00
imd.h
inttypes.h
ip_checksum.h
kconfig.h
lib.h lib: remove ulzma() 2016-07-01 23:55:16 +02:00
main_decl.h arches: lib: add main_decl.h for main() declaration 2016-02-11 23:29:08 +01:00
memlayout.h memlayout: Ensure TIMESTAMP() region is big enough to avoid BUG() 2016-08-23 21:33:29 +02:00
memory_info.h
memrange.h lib/memrange: add function to initialize range_entry 2016-03-09 16:46:16 +01:00
nhlt.h lib/nhlt: drop nhlt_soc_add_endpoint() 2016-06-29 23:15:37 +02:00
option.h
program_loading.h arm64: Use 'payload' format for ATF instead of 'stage' 2016-10-06 21:49:52 +02:00
reg_script.h lib/reg_script: Add display support 2016-05-04 19:21:40 +02:00
reset.h src/include: Improve code formatting 2016-09-05 12:28:32 +02:00
rmodule.h src/include: Capitalize CPU, RAM and ROM 2016-07-31 18:30:16 +02:00
romstage_handoff.h
rtc.h lib: Add real-time-clock functions 2016-06-24 20:22:05 +02:00
rules.h arch/arm: Add armv7-r configuration 2016-09-12 19:58:43 +02:00
sdram_mode.h
smbios.h src/include: Add space around operators 2016-09-20 17:38:56 +02:00
spd.h SPD: Add CAS latency 2 2016-07-12 15:17:31 +02:00
spd_cache.h
spd_ddr2.h src/include: Add space around operators 2016-09-20 17:38:56 +02:00
spi-generic.h
spi_flash.h
stage_cache.h
stddef.h stddef.h: fix zeroptr's definition 2016-04-15 16:18:57 +02:00
stdlib.h
string.h src/include: Improve code formatting 2016-09-05 12:28:32 +02:00
swab.h
symbols.h memlayout: Add symbols for stage bounds 2016-02-22 21:38:07 +01:00
thread.h
timer.h
timestamp.h
tpm.h
trace.h
types.h
vbe.h src/include: Add space around operators 2016-09-20 17:38:56 +02:00
version.h
watchdog.h src/include: Improve code formatting 2016-09-05 12:28:32 +02:00
wrdd.h Remove extra newlines from the end of all coreboot files. 2016-07-31 18:19:33 +02:00