coreboot-kgpe-d16/src
Jonathan Neuschäfer 50b74b2a27 arch/riscv: Update comment about mstatus initialization
coreboot does not set up virtual memory anymore.

Change-Id: I231af07b2988e8362d1cdd606ce889fb31136ff1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-10-06 21:30:32 +00:00
..
acpi
arch arch/riscv: Update comment about mstatus initialization 2018-10-06 21:30:32 +00:00
commonlib complier.h: add __always_inline and use it in code base 2018-09-14 08:16:37 +00:00
console console: Enable CONSOLE_USB by default 2018-10-04 13:08:50 +00:00
cpu src: Fix MSR_PKG_CST_CONFIG_CONTROL register name 2018-10-05 01:38:15 +00:00
device src/device/device.c: Don't use device_t in ramstage 2018-09-19 10:35:01 +00:00
drivers drivers/generic: Add support for providing DSD properties 2018-10-06 00:02:12 +00:00
ec ec/google/chromeec: Define a sync IRQ if needed 2018-10-04 09:36:59 +00:00
include src: Fix MSR_PKG_CST_CONFIG_CONTROL register name 2018-10-05 01:38:15 +00:00
lib src/lib/edid.c: Replace #if 1 with something useful 2018-10-05 01:45:46 +00:00
mainboard mb/emulation/*-riscv: Remove "UCB" from RISC-V board names 2018-10-06 21:30:18 +00:00
northbridge src/*: normalize Google copyright headers 2018-09-28 07:13:00 +00:00
security tpm2/tlcl_send_startup: correct TPM2_Startup error logic 2018-10-05 03:47:22 +00:00
soc soc/intel/common, mb/google, mb/siemens: Use lower case x for RXD 2018-10-06 00:18:25 +00:00
southbridge sb/amd/pi/hudson: Remove #if 1 2018-10-04 09:40:06 +00:00
superio superio/ite/it8721f: Add SuperIO ACPI declarations 2018-08-21 14:45:36 +00:00
vendorcode vendorcode/amd/pi/00670F00/Lib: Remove folder 2018-09-28 10:15:22 +00:00
Kconfig src/Kconfig: Drop a superfluous word 2018-10-01 15:28:47 +00:00