coreboot-kgpe-d16/src
Julius Werner 73d042bd90 vboot: Disallow separate verstage after romstage, try to clarify logic
No board has ever tried to combine CONFIG_SEPARATE_VERSTAGE with
CONFIG_VBOOT_STARTS_IN_ROMSTAGE. There are probably many reasons why
this wouldn't work (e.g. x86 CAR migration logic currently always
assumes verstage code to run pre-migration). It would also not really
make sense: the reason we use separate verstages is to decrease
bootblock size (mitigating the boot speed cost of slow boot ROM SPI
drivers) and to allow the SRAM-saving RETURN_FROM_VERSTAGE trick,
neither of which would apply to the after-romstage case. It is better to
just forbid that case explicitly and give programmers more guarantees
about what the verstage is (e.g. now the assumption that it runs pre-RAM
is always valid).

Since Kconfig dependencies aren't always guaranteed in the face of
'select' statements, also add some explicit compile-time assertions to
the vboot code. We can simplify some of the loader logic which now no
longer needs to provide for the forbidden case. In addition, also try to
make some of the loader logic more readable by writing it in a more
functional style that allows us to put more assertions about which cases
should be unreachable in there, which will hopefully make it more robust
and fail-fast with future changes (e.g. addition of new stages).

Change-Id: Iaf60040af4eff711d9b80ee0e5950ce05958b3aa
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18983
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-03-28 22:17:35 +02:00
..
acpi src/acpi: Capitalize ACPI and SATA 2016-07-31 19:25:40 +02:00
arch vboot: Remove CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL Kconfig option 2017-03-28 22:14:03 +02:00
commonlib commonlib: Wrap lines at 80 columns 2017-03-13 21:23:21 +01:00
console console: Enable do_printk_va_list for VBOOT 2016-12-27 18:07:39 +01:00
cpu AGESA: Fork for new cache-as-ram init code 2017-03-28 01:57:37 +02:00
device device/dram/ddr2: Add common ddr2 spd decoder 2017-03-10 11:17:27 +01:00
drivers soc/intel/common/block: Add cache as ram init and teardown code 2017-03-28 16:38:42 +02:00
ec ec: Use EC_ENABLE_LID_SWITCH for all mainboards with LID using chromeec 2017-03-27 03:03:16 +02:00
include vboot: Disallow separate verstage after romstage, try to clarify logic 2017-03-28 22:17:35 +02:00
lib chromeos: Remove old MOCK_TPM references 2017-03-28 22:12:05 +02:00
mainboard chromeos / broadwell / jecht: Make save_chromeos_gpios() jecht-specific 2017-03-28 22:16:24 +02:00
northbridge vboot: Select SoC-specific configuration for all Chrome OS boards 2017-03-28 22:12:54 +02:00
soc chromeos / broadwell / jecht: Make save_chromeos_gpios() jecht-specific 2017-03-28 22:16:24 +02:00
southbridge southbridge/intel/i82801gx: Fix problems found by checkpatch.pl 2017-03-22 17:55:53 +01:00
superio superio/fintek: Add support for Fintek F71808A 2017-03-27 19:19:56 +02:00
vboot vboot: Disallow separate verstage after romstage, try to clarify logic 2017-03-28 22:17:35 +02:00
vendorcode chromeos / broadwell / jecht: Make save_chromeos_gpios() jecht-specific 2017-03-28 22:16:24 +02:00
Kconfig GDB_WAIT: Clarify Kconfig description 2017-03-14 22:20:47 +01:00