Arthur Heymans 77d5e7481b nb/intel/haswell: Add an option for where verstage starts ... Previously Haswell used a romcc bootblock and starting verstage in romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also possible to have a separate verstage. This selects using a separate verstage by default but still keeps the option around to use verstage in romstage. Also make sure mrc.bin is only added to the COREBOOT fmap region as it requires to be run at a specific offset. This means that coreboot will have to jump from a RW region to the RO region for that binary and back to that RW region after that binary is done initializing the memory. Change-Id: I3b7b29f4a24c0fb830ff76fe31a35b6afcae4e67 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26926 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2019-04-21 23:32:37 +00:00
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bd82x6x	nb/intel/sandybridge: Move southbridge code to bd82x6x	2019-04-18 09:57:51 +00:00
common	nb/intel/haswell: Add an option for where verstage starts	2019-04-21 23:32:37 +00:00
fsp_rangeley	src: Use include <delay.h> when appropriate	2019-04-06 16:09:12 +00:00
i82371eb	src: Use 'include <string.h>' when appropriate	2019-03-20 20:27:51 +00:00
i82801dx	sb/intel/{common,i82801dx}: Improve TCO debug code	2019-04-07 02:43:26 +00:00
i82801gx	sb/intel/i82801gx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB	2019-04-13 14:49:31 +00:00
i82801ix	sb/intel/i82801ix: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB	2019-04-16 08:58:41 +00:00
i82801jx	sb/intel/i82801jx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB	2019-04-13 14:49:01 +00:00
i82870	arch/io.h: Drop unnecessary include	2019-03-04 15:08:03 +00:00
ibexpeak	Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX)	2019-03-25 11:03:49 +00:00
lynxpoint	nb/intel/haswell: Add an option for where verstage starts	2019-04-21 23:32:37 +00:00