Subrata Banik 913ea97fbe soc/intel: Select GMA v2 for ADL, MTL, TGL to reflect port/pipe defs ... Intel GFX IP TRANS_DDI_FUNC_CTL register bit definitions have changed since Tiger Lake. This register is used to map ports and pipes to display controllers, so reflecting the correct status is important for detecting physical display end point devices. This patch ensures that ADL, MTL, and TGL SoCs choose GMA version 2 to properly reflect the updated port and pipe register definitions. BUG=b:299137940 TEST=Build and boot google/rex successfully. Change-Id: Ie2082747d18a5f136f410b1019be4d6c801617b1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com>		2023-10-04 18:50:32 +00:00
..
amd	soc/amd: rework SPL file override and SPL fusing handling	2023-10-04 09:34:54 +00:00
cavium	soc/cavium: Use weak over attrbute__((weak))	2023-09-14 14:40:37 +00:00
example/min86	soc: Remove SOC_SPECIFIC_OPTIONS	2023-08-21 23:45:43 +00:00
intel	soc/intel: Select GMA v2 for ADL, MTL, TGL to reflect port/pipe defs	2023-10-04 18:50:32 +00:00
mediatek	soc/mediatek/mt8188: devapc: Add SCP domain setting	2023-10-02 06:32:10 +00:00
nvidia	soc/nvidia: Remove space between function name and '('	2023-09-11 15:51:44 +00:00
qualcomm	qualcomm/common: Remove carriage returns from QcLib log	2023-09-14 23:53:54 +00:00
rockchip
samsung	soc/samsung/exynos5250/clock: Remove space before semicolon	2023-08-20 22:00:03 +00:00
sifive/fu540	soc/sifive/fu540: Remove space after a cast	2023-09-19 13:13:27 +00:00
ti
ucb/riscv