coreboot-kgpe-d16/src/soc
Jeremy Compostella 79c09ba3b6 soc/intel/mtl: Display Sign-of-Life message using FSP-M
Meteor Lake Firmware Support Package (FSP-M) for ChromeOS includes an
pre-memory graphics driver which can be leveraged to display a text
message thanks to the following FSP-M UPD (Updateable Product Data):

- VgaInitControl (bitfield):

  Bit 0: Turn on graphics, setup VGA text mode and display
         `VgaMessage' text centered on the screen.

  Bit 1: Clear text and tear down VGA text mode and graphics before
         returning from FSP-M.

- VbtPtr (address): Pointer to the VBT (Video BIOS Tables) binary.

- VbtSize (unsigned int): Size of the VBT binary.

- LidStatus (boolean): Due to limited resources at early boot stages,
  the text message is displayed on a single monitor. The lid status
  helps decide which display is the most appropriate.

  0: Lid is closed: show the text message on the external display if
     available, do not display anything otherwise.

  1: Lid is open: show the message on the internal display if
     available, use an external display if available otherwise.

- VgaMessage (string): Text message to display.

If the `SOC_INTEL_METEORLAKE_SIGN_OF_LIFE' flag is set, coreboot
configures the UPDs above to display a text message during memory
training and CSME update. The text message can be configured via the
locale text mechanism using the `memory_training_desc' name.

The `SOC_INTEL_METEORLAKE_SIGN_OF_LIFE' selects the LZ4 compression
algorithm for VBT because LZMA decompression is not available in
romstage by default and adding LZMA support increases the romstage
binary size more than the VBT binary is reduced.

BUG=b:279173035
TEST=Text message is displayed during memory training on a rex board

Change-Id: I8e7772582b1895fa8e38780932346683be998558
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78244
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-11 05:07:23 +00:00
..
amd soc/amd/common: Move PCIe CLKREQ programming under fsp 2023-12-06 19:12:59 +00:00
cavium Revert "Kconfig: Bring HEAP_SIZE to a common, large value" 2023-11-07 17:35:39 +00:00
example/min86 soc: Remove SOC_SPECIFIC_OPTIONS 2023-08-21 23:45:43 +00:00
intel soc/intel/mtl: Display Sign-of-Life message using FSP-M 2023-12-11 05:07:23 +00:00
mediatek soc/mediatek/mt8188: devapc: Allow APU to access BND_NORTH_APB2_S 2023-12-04 16:48:33 +00:00
nvidia memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere 2023-10-11 12:08:22 +00:00
qualcomm qualcomm/sc7180: Move QCSDI and increase romstage size by 4KB 2023-11-18 00:41:53 +00:00
rockchip fmap: Map less space in fallback path without CBFS verification 2023-11-13 14:19:01 +00:00
samsung memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere 2023-10-11 12:08:22 +00:00
sifive/fu540 memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere 2023-10-11 12:08:22 +00:00
ti
ucb/riscv