V Sowmya 7aee5c67a1 soc/intel/jasperlake: Add FSP UPDs for minimum assertion widths ... Add the FSP UPDs for the chipset minimum assertion widths and Power cycle duration to the chip options which can be configured per mainboard. * PchPmSlpS3MinAssert: SLP_S3 Minimum Assertion Width Policy * PchPmSlpS4MinAssert: SLP_S4 Minimum Assertion Width Policy * PchPmSlpSusMinAssert: SLP_SUS Minimum Assertion Width Policy * PchPmSlpAMinAssert: SLP_A Minimum Assertion Width Policy * PchPmPwrCycDur: PCH PM Reset Power Cycle Duration * Check to avoid violating the PCH EDS recommendation for the PchPmPwrCycDur setting. BUG=b:159104150 Change-Id: I042e8e34b7dfda3bc21e5f2e6727cb7692ffc7f7 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>		2020-08-17 05:14:05 +00:00
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apollolake	soc/intel/apollolake: Rename UART irqs	2020-08-10 10:45:46 +00:00
baytrail	{sb,soc}/intel/*/acpi/lpc.asl: Drop commented-out code	2020-08-05 15:46:17 +00:00
braswell	{sb,soc}/intel/*/acpi/lpc.asl: Drop commented-out code	2020-08-05 15:46:17 +00:00
broadwell	soc/intel/broadwell/iobp: Log success in pch_iobp_write()	2020-08-07 11:57:32 +00:00
cannonlake	soc/intel/cannonlake: Set FSP-M UPD Heci1BarAddress	2020-08-12 17:39:49 +00:00
common	soc/intel/common/cse_lite: Perform a board specific reset	2020-08-14 08:34:21 +00:00
denverton_ns	cpu,soc/intel: Drop select SMP	2020-07-26 20:59:52 +00:00
icelake	soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming	2020-08-09 11:03:37 +00:00
jasperlake	soc/intel/jasperlake: Add FSP UPDs for minimum assertion widths	2020-08-17 05:14:05 +00:00
quark	src: Make HAVE_CF9_RESET set the FADT reset register	2020-07-20 13:23:13 +00:00
skylake	soc/intel/skylake: Refactor PEG configuration	2020-08-14 21:57:09 +00:00
tigerlake	soc/intel/tigerlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 5KB	2020-08-14 23:06:08 +00:00
xeon_sp	soc/intel/xeon_sp/cpx: add VT-d support	2020-08-14 09:08:24 +00:00
Kconfig	fsp2_0: Gather Kconfig declarations	2020-04-05 23:26:24 +00:00