Michael Niewöhner 89e83b76b4 soc/intel/common/block/acpi: add Kconfig for CPPC entries generation ... Change-Id: Ieae9f221ffb27cf52cab21a130e18aa3929caea3 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47540 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-11-13 18:42:49 +00:00
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alderlake	soc/intel/alderlake: Add PCH ID 0x5181	2020-11-12 03:51:49 +00:00
apollolake	soc/intel: Use of common reset code block	2020-11-02 10:43:53 +00:00
baytrail	src: Include <arch/io.h> when appropriate	2020-10-26 06:44:40 +00:00
braswell	src: Include <arch/io.h> when appropriate	2020-10-26 06:44:40 +00:00
broadwell	soc/intel/broadwell: Split up acpi.c	2020-11-13 13:26:02 +00:00
cannonlake	soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig	2020-11-13 17:32:37 +00:00
common	soc/intel/common/block/acpi: add Kconfig for CPPC entries generation	2020-11-13 18:42:49 +00:00
denverton_ns	soc/intel/denverton_ns: Add PCH_DEVFN_PMC for finding PMC device	2020-11-02 06:28:50 +00:00
elkhartlake	soc/intel/*/chip: Remove unused devicetree entry	2020-11-09 07:27:38 +00:00
icelake	soc/intel/*/chip: Remove unused devicetree entry	2020-11-09 07:27:38 +00:00
jasperlake	soc/intel/jasperlake: Log PM event from an internal device	2020-11-10 06:20:04 +00:00
quark	arch/x86: Introduce ARCH_ALL_STAGES_X86_32	2020-09-26 11:42:28 +00:00
skylake	soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig	2020-11-13 17:32:37 +00:00
tigerlake	mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS	2020-11-11 20:44:31 +00:00
xeon_sp	soc/intel/xeon_sp: Tidy up adding MADT ioapic entries	2020-11-13 00:24:46 +00:00
Kconfig	fsp2_0: Gather Kconfig declarations	2020-04-05 23:26:24 +00:00