coreboot-kgpe-d16/src/soc/intel/tigerlake
Shreesh Chhabbi 42b1d3fccf mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS
Selecting USE_CAR_NEM_ENHANCED_V1 as of now. This selection in Kconfig
programs IA32_L3_MASK_1 (0xc91) & IA32_L3_MASK_2 (0xc92). These will
select ways for eviction & non-eviction. TGL will have to switch back
to USE_CAR_NEM_ENHANCED_V2 once the IA32_L3_SF_MASK_1 (0x1891) &
IA32_L3_SF_MASK_2 (0x1892) programming requirements are understood.

Bug=b:171601324
BRANCH=volteer
Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ifc77856e26ab26f9fbb2693f70c751f43337421b
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-11 20:44:31 +00:00
..
acpi soc/intel/tigerlake: Enable and use USB4 PCIe driver 2020-10-14 02:55:35 +00:00
bootblock soc/intel/tigerlake: Rename pch_init() code 2020-08-26 07:36:21 +00:00
include/soc {cpu,soc}/intel: deduplicate cpu code 2020-10-24 09:46:45 +00:00
romstage soc/intel: remove duplicate weak versions of mainboard_get_dram_part_num() 2020-10-05 18:03:22 +00:00
spd util: Add DDR4 generic SPD for H5ANAG6NCJR-XNC 2020-10-12 08:38:27 +00:00
acpi.c soc/intel/tigerlake: Simplify is-device-enabled checks 2020-07-28 08:36:59 +00:00
chip.c soc/intel/tigerlake: Enable TCSS XHCI device and define port aliases 2020-10-30 18:34:30 +00:00
chip.h soc/intel/*/chip: Remove unused devicetree entry 2020-11-09 07:27:38 +00:00
chipset.cb mb, soc/intel: Reorganize CNVi device entries in devicetree 2020-11-02 06:15:06 +00:00
cpu.c soc/intel: deduplicate ACPI timer emulation 2020-10-28 21:28:19 +00:00
elog.c soc/intel/tigerlake: Log PM event from an internal device 2020-11-10 06:20:19 +00:00
espi.c soc/intel: Move pch_misc_init() to common code 2020-10-03 04:19:00 +00:00
finalize.c src: Include <arch/io.h> when appropriate 2020-10-26 06:44:40 +00:00
fsp_params.c soc/intel/tigerlake: Disable C1 C-state Demotion 2020-11-05 22:58:27 +00:00
gpio.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
gspi.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
i2c.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
Kconfig mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS 2020-11-11 20:44:31 +00:00
lockdown.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
Makefile.inc soc/intel/tigerlake: Log PM event from an internal device 2020-11-10 06:20:19 +00:00
me.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
meminit.c soc/intel/tigerlake: Reflow long lines 2020-10-19 06:47:30 +00:00
p2sb.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
pmc.c soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers 2020-10-30 15:23:34 +00:00
pmutil.c src/soc/intel: Drop unneeded empty lines 2020-09-21 16:15:25 +00:00
reset.c soc/intel: Use of common reset code block 2020-11-02 10:43:53 +00:00
smihandler.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
smmrelocate.c soc/intel/tigerlake: Add SMRR Locking support 2020-09-08 05:25:34 +00:00
soundwire.c soc/intel/tigerlake: Provide SoundWire controller properties 2020-05-22 01:48:39 +00:00
spi.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
systemagent.c soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKU 2020-07-25 00:07:36 +00:00
uart.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
xhci.c soc/intel/tigerlake: Log PM event from an internal device 2020-11-10 06:20:19 +00:00