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coreboot-kgpe-d16/src/soc/rockchip/rk3399
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Caesar Wang 905a933f46 rockchip/rk3399: protect the DRAM address for atf 
We need ensure the bl31 base is greater than 4KB since there's
the shared mem for coreboot.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=boot to kernel with atf patch

Change-Id: I44cf436b3072f03b93da4a19227dcc540d7513db
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a462f604c284c84bd8c5a0420e75eeae5035b382
Original-Change-Id: I55ec134762bb6bcbc91937ad5763617d7488490b
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/342334
Original-Commit-Ready: Vadim Bendebury <vbendeb@google.com>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: Vadim Bendebury <vbendeb@google.com>
Reviewed-on: https://review.coreboot.org/14741
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:51:34 +02:00
..
include/soc rockchip: rk3399: support saradc 2016-05-09 08:46:42 +02:00
bootblock.c rockchip: rk3399: init the secure setting 2016-05-09 08:44:52 +02:00
clock.c rockchip: rk3399: support saradc 2016-05-09 08:46:42 +02:00
gpio.c rockchip: rk3399: add gpio driver 2016-05-09 08:43:54 +02:00
Kconfig rockchip: rk3399: enable arm trust firmware 2016-05-09 08:46:20 +02:00
Makefile.inc google/gru: enable pp1500 and pp3000 rails as soon as possible 2016-05-09 08:50:16 +02:00
mmu_operations.c rockchip: rk3399: enable mmu 2016-05-09 08:42:04 +02:00
romstage.c rockchip/rk3399: Set all 4 DVFS voltage rails to 1.1V @300kHz 2016-05-09 08:49:24 +02:00
saradc.c rockchip: rk3399: support saradc 2016-05-09 08:46:42 +02:00
sdram.c rockchip: rk3399: add sdram driver 2016-05-09 08:45:13 +02:00
soc.c rockchip/rk3399: protect the DRAM address for atf 2016-05-09 08:51:34 +02:00
timer.c