We need ensure the bl31 base is greater than 4KB since there's
the shared mem for coreboot.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=boot to kernel with atf patch
Change-Id: I44cf436b3072f03b93da4a19227dcc540d7513db
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a462f604c284c84bd8c5a0420e75eeae5035b382
Original-Change-Id: I55ec134762bb6bcbc91937ad5763617d7488490b
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/342334
Original-Commit-Ready: Vadim Bendebury <vbendeb@google.com>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: Vadim Bendebury <vbendeb@google.com>
Reviewed-on: https://review.coreboot.org/14741
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The idea is that they stay low unless we know that we booted from SPI
flash. As this code runs in SPI flash - it is ok to turn these rails
on as soon as possible, and pp3000 rail it is essential for UART to
work.
Kevin rev1 and Gru designs are going to be using these pins to
control these rails. Kevin rev1 had those GPIO pins routed to two
chip enable signals, it is save to assert them high.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=kevin rev0 still boots (which does not prove much)
TEST=run coreboot on kevin rev1 to kernel
Change-Id: I5f3eb4cf5d6f04a0253574dd8b5c039eab0bae1a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 987042246672e9391087dbd5060785a379dde131
Original-Change-Id: I31bb03334ad9e3aa57db726fb43dec85014a3f05
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/341543
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://review.coreboot.org/14729
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Previous code had several problems:
* It was only initting 3 of the 4 voltage rails hooked up to PWM
regulators.
* It was using a PWM frequency that was out of range. Apparently from
testing 300kHz is best.
* It was initting all rails to .9V. On my Kevin I needed 1.1V to make
booting all 6 cores / rebooting reliable.
With this fix both booting all 6 cores in the kernel is reliable (if we
tell the kernel not to touch the PWM) and the "reboot" command from
Linux userspace is also reliable (previously it crashed in coreboot).
NOTES:
* Setting all rails to the same voltage doesn't make a lot of sense. We
should figure out what these should _actually_ be. Presumably the
little CPU rail can be lower, at least. ...and we don't use the GPU
in the BIOS so we should set that lower.
BRANCH=none
BUG=chrome-os-partner:51922
TEST=reboot test
Change-Id: I44f6394e43d291cccf3795ad73ee5b21bd949766
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0ac79a7cfb079d23c9d7c4899fdf18c87d05ed0e
Original-Change-Id: I80996adefd8542d53ecce59e5233c553700b309f
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/339151
Reviewed-on: https://review.coreboot.org/14727
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch add functions to configure saradc clk and get
saradc's raw value for each channel.
Currently add saradc to ramstage.
Please refer to TRM V0.3 Part 2 Chapter 18 for this IP.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=on kevin board, get the raw value 61 for channel 0,
measure the ADC_IN0 as 0.109V,
61.0/1024 = 0.05957 0.109V/1.8V = 0.06056
Change-Id: Ic198b2a964ccf8bb687441f0e2702665402fff6e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bc400316de2d75eccad3990a4187bf2dc49a844a
Original-Change-Id: I542430ed97bd27f9bfcec89b1d703d9fa390d4e0
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/334177
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14720
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The base address of MMIO space is different for different Rockchip
SOCs. Define them in the appropriate address map files and use the
definition in common code.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=emerge-kevin coreboot
Change-Id: I615f3cadd6d5d994b7dd1defbd10d02ad5c994da
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 24f941e960e4a2cfb9fc26415f56e240de3d00d9
Original-Change-Id: Ia48d75e7de546b17636cde7829ee09837b9d7ac9
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/337190
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14717
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add the sdram driver for rk3399. With this patch we can boot
into depthcharge.
This patch also include a config file for lpddr3-hynix-4GB
that generated bases on its datasheet.
Please refer to TRM V0.3 Part1 Chapter 9 for DMC.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=boot to depthcharge on kevin
Change-Id: I2afcaa3b68dbad77a5fe677b835289b675ed2bef
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5d777e29942057fb7237eefa34051d1f54b19405
Original-Change-Id: Ifa1fe98a7058869518757d50678a64620610d91d
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/332562
Reviewed-on: https://review.coreboot.org/14716
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
set sdram, sram and all device to non-secure status,
so we can free to do mmu operation in coreboot. bl31
will care about secure control.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=emerge-kevin coreboot
Change-Id: I11e02246550630c6dfe4e0cbad01e8cd5b83ef1e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ae2df532856110c4d87eb162fd3687f8de27c77f
Original-Change-Id: Ia026cf685a9d7bdf7b0c7181b1b325c54bc4554f
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/338947
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14715
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reuse the common gpio driver and implement some stubs
in gpio.h.
RK3288 has one pmu gpio while RK3399 have two.
Please refer to TRM V0.3 Part2 Chapter 11 for GPIO section.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=emerge-kevin coreboot
Change-Id: I041865ce269b0ae1f6a07e6c37d53d565a37c5ef
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d416ba0ce6a1ff2cf52f6b83ade601d93b40ffeb
Original-Change-Id: I1d213a91ea508997b876441250743671204d7c53
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/332560
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14713
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch add i2c clock driver and reuse the common
rockchip i2c driver.
The i2c0,4,8 src clock from ppll, while i2c1,2,3,5,6,7 from gpll.
Please refer to TRM V0.3 Part1 Page 142 for i2c clock setting.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=emerge-kevin coreboot
Change-Id: I91822e483244d71798a1c68f14ba0a84f405a665
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 270118e44d159f6a27812fa234b34fe7ac54cbe4
Original-Change-Id: Iea5f4a93cf173e1278166dcb04e19a4ef6c4af04
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/338948
Reviewed-on: https://review.coreboot.org/14711
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch implements spi clock driver and initialize
SPI flash rom for the baseboard gru.
There are 6 on-chip SPI controllers inside RK3399. For
SPI3, it's source clk from ppll, while the others from gpll.
Please refer to CRU session of TRM for detail.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=emerge-kevin coreboot
Change-Id: I597ae2cc8ba1bfaefdfbf6116027d009daa8e049
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4c6a9b0aedd427727ed4f4a821c5c54fb3a174b9
Original-Change-Id: I68ad859bf4fc5dacaaee5a2cd33418c729cf39b8
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/338946
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14710
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch initialize MMU and config mmu ranges for rk3399.
During the bootblock phase, mark the max dram size supported(4GiB)
as device memory because the mmio space start at 0xF8000000, and
_sram as secure memory.
After ddr setup in romstage, remark whole dram as cached memory
except the _dma_coherent range.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=emerge-kevin coreboot
Change-Id: I0cd4abb8c30b73d87d8ba6f964edd42bdf4813fb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fc22ab0c16d8107c217db1629286d5ff1c4bc5b3
Original-Change-Id: I66bfde396036d7a66b29517937a28f0767635066
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/332387
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14708
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch list four frequencies for ddr controller,
200MHz, 300MHz, 666MHz and 800MHz and configure
each freq by setting the DPLL dividers.
By default, the clk_ddrc is from DPLL and equals to DPLL,
so here we only need to set the DPLL clock.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=emerge-kevin coreboot
Change-Id: Ifabe85b5dc95e3c8e3e9cbf946e12e8b06b881cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 18ec4f7d8738472fbadd60fa3c8f810f5347ffa2
Original-Change-Id: I448057542c3885068ddffa5b37d0341ee3ec04b1
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/340184
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14707
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch initialize the PLL clocks and add function to
configure cpu freq. Right now, we set the little cpu freq to 600MHz.
In coreboot, we currently care about these four PLLs,
o. APLL for cpu clk, where A stands for AXI,
o. CPLL and GPLL are the generic PLL mainly for peripheral clk,
o. PPLL is only PMU clk.
For the peripheral clocks, there are thress clocks named as,
aclk_perihp,
aclk_perilp0,
hclk_perilp1,
where the 'h' and 'l' letters refer to High and Low speed.
As the diagram below, the aclk_perihp always be the parent of
more higher speed peripheral devices like pcie, and
hclk_perilp1 for spi, i2c, aclk_perilp0 for crypto.
These three clocks can choose parent from GPLL or CPLL freely,
in this patch, they are all sourced from GPLL.
GPLL(594M)/CPLL(384M) APLL(600M for little core)
| |
`-- aclk_perihp `-- clk_core(600M == APLL)
| | |
| `-- periph_aclk(148.5M) `-- atclk_core(300M)
| `-- periph_hclk(148.5M) `-- aclkm_core(300M)
| `-- periph_pclk(37.125M) `-- pclk_dbg_core(100M)
|
`-- hclk_perilp1
| |
| `-- periph_hclk(99M) PPLL(594M)
| `-- periph_pclk(49.5M) |
| `-- pmu_pclk(99M)
`-- aclk_perilp0
|
`-- periph_aclk(99M)
`-- periph_hclk(99M)
`-- periph_pclk(49.5M)
BRANCH=none
BUG=chrome-os-partner:51537
TEST=emerge-kevin coreboot
Change-Id: I1c46ff17e6b466529244afb41d7fd4abbcfd3da4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9f0d31177336a3450577950426f9cc9d56e2254c
Original-Change-Id: I4ad00df3e406bd0a7576287d6e62b8993a8c2d02
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/332386
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14706
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Quoting an earlier review comment, using static structures pointers in
the include file "should allow the compiler to optimize accesses
better than defining it in a separate compilation unit (by being able
to constant fold stuff like &rk3399_pmusgrf->field into a single
address, rather than loading the symbol, loading an offset constant
and adding)".
Any decent compiler linker system nowadays would consolidate this
definition in any case.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the rest of the patches applied Kevin successfully boots
Linux kernel.
Change-Id: Ibb576c7691a30f2f429651fcca133bd72710c13b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 89b6f22e37f733667156f15afb8c27d8a9f07512
Original-Change-Id: Ice8d6d766a91e7f4fce553378a23b9ca593d12dd
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/339869
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14705
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The GRF(general register file) of rk3399 is divided into two sections,
o. GRF, used for general non-secure system
o. PMUGRF, used for always-on syosyem
This patch defines the registers used for iomux/gpio/system control.
BRANCH=none
BUG=none
TEST=emerge-kevin coreboot
Change-Id: I3239793523e0f55f6661ef029c3dac9970990fb8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 897d01573ea2bbe2b3091358ec3c9728ee82f8ec
Original-Change-Id: I4c228ddb60c9c4056de50312dc269227fac9a7fa
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/332388
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14704
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch is only to make building happy, the real sdram driver
comes later.
BRANCH=none
BUG=none
TEST=emerge-kevin coreboot
Change-Id: I4123c3a6627d7264c615fefbb89e16c4dfb9a423
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5b992a7895a72c83f57228d3abd1ae37d55e7e7b
Original-Change-Id: Ie340877e828ae760169ccfa9a7099e7472d2fc26
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/338944
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14703
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The standard uart8250mem_32 driver is now usable on ARM, so use it.
BUG=none
BRANCH=none
TEST=see that serial firmware builds still log on serial in all stages
on veyron_minnie. Also verified that a 9600 baud console is functional.
Change-Id: I653b70a0d51a8d136e1da17537988f5b33c7a160
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fa27c60fd38002775072d11fca431d4788b4d1d7
Original-Change-Id: I047d74ac2d5c311f303955e62391114e16ec087a
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/337551
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14319
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
To avoid diverging too much on an actively developed code base, keep
the changes to a separate commit that can be downstreamed more easily:
- removed unused includes
- gave kevin board a "Kevin" part number
- marked RW_LEGACY as CBFS region (to follow up upstream changes)
- moved romstage entry point to SoC code (instead of encouraging
per-board copy pasta)
Change-Id: Ief0c8db3c4af96fe2be2e2397d8874ad06fb6f1f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14362
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Most things still need to be filled in, but this will allow
us to build boards which use this SOC.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the rest of the patches applied Kevin board can be booted to
Linux login propmt.
Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 27dfc39efe95025be2271e2e00e9df93b7907840
Original-Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/332385
Reviewed-on: https://review.coreboot.org/13915
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
