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coreboot-kgpe-d16/src/soc/intel/common
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Lijian Zhao ad1e49afac soc/intel/common: Limit BIOS region cache to 16MB 
Cache BIOS region can boost boot performance, however it can't be over
16MB, according to processor EDS vol1(Apollolake/Skylake/WhiskeyLake),
FLASH+APIC LT will be less than 20MB under 4G. Set the maxiam to 16GB
to save numbers of mtrr entries.

BUG=b:119267832
TEST=Build and boot up fine on whiskeylake rvp platform.

Change-Id: I46a47c8bf66b14fb2fcb7b6b1d30d02886c450a4
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/29944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-04 23:29:28 +00:00
..
acpi soc/intel/common/dptf: Add method for temp conversion 2018-12-04 10:19:57 +00:00
basecode soc/intel/common: Make infrastructure ready for Intel common stage files 2018-06-21 15:54:48 +00:00
block soc/intel/common: Limit BIOS region cache to 16MB 2018-12-04 23:29:28 +00:00
pch soc/intel/common/*/Kconfig: Remove redundant comments 2018-11-18 20:57:28 +00:00
acpi.h
acpi_wake_source.c Move compiler.h to commonlib 2018-10-08 16:57:27 +00:00
hda_verb.c
hda_verb.h
Kconfig soc/intel/common: Bring DISPLAY_MTRRS into the light 2018-11-23 08:34:16 +00:00
Makefile.inc soc/intel/common: Bring DISPLAY_MTRRS into the light 2018-11-23 08:34:16 +00:00
mma.c Move compiler.h to commonlib 2018-10-08 16:57:27 +00:00
mma.h
nhlt.c
reset.c intel: Use CF9 reset (part 2) 2018-10-22 08:35:32 +00:00
reset.h intel: Use CF9 reset (part 2) 2018-10-22 08:35:32 +00:00
smbios.c
smbios.h
tpm_tis.c security/tpm: Change TPM naming for different layers. 2018-01-18 01:45:35 +00:00
vbt.c src: Remove unneeded include <cbfs.h> 2018-11-16 10:26:32 +00:00
vbt.h drivers/intel/gma, soc/intel/common: improve cooperation 2018-05-09 13:48:07 +00:00