Lijian Zhao b3dfcb863c soc/intel/cannonlake: Enable common PMC code for CNL ... This update changes Cannonlake to use the new common PMC code. This will help to reduce code duplication and streamline code bring up. Change-Id: Ia69fee8985e1c39b0e4b104c51439bca1a5493ac Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2017-08-21 20:37:57 +00:00
..
bootblock	soc/intel/cannonlake: Enable common PMC code for CNL	2017-08-21 20:37:57 +00:00
include/soc	soc/intel/cannonlake: Enable common PMC code for CNL	2017-08-21 20:37:57 +00:00
romstage	soc/intel/cannonlake: Enable common PMC code for CNL	2017-08-21 20:37:57 +00:00
cbmem.c
chip.c	intel/cannonlake/chip: Add initial PCI enum support	2017-08-17 19:23:48 +00:00
chip.h	soc/intel/cannonlake: Enable common PMC code for CNL	2017-08-21 20:37:57 +00:00
gpio.c	soc/intel/cannonlake: Correct gpio definition	2017-07-27 15:50:36 +00:00
gspi.c	soc/intel/cannonlake: Add SPI flash controller driver	2017-08-17 21:50:58 +00:00
Kconfig	soc/intel/cannonlake: Enable common PMC code for CNL	2017-08-21 20:37:57 +00:00
Makefile.inc	soc/intel/cannonlake: Enable common PMC code for CNL	2017-08-21 20:37:57 +00:00
memmap.c	soc/intel/cannonlake: Add memory map support	2017-08-07 17:53:13 +00:00
pmutil.c	soc/intel/cannonlake: Enable common PMC code for CNL	2017-08-21 20:37:57 +00:00
reset.c	soc/intel/cannonlake: Initialize struct member to 0	2017-08-14 17:58:50 +00:00
smihandler.c	soc/cannonlake: Enable SMM code for Cannon Lake	2017-08-11 16:04:42 +00:00
spi.c	soc/intel/cannonlake: Add SPI flash controller driver	2017-08-17 21:50:58 +00:00
systemagent.c	soc/intel/cannonlake: Add ramstage SystemAgent support	2017-08-09 20:06:27 +00:00
uart.c	soc/intel/cannonlake: Add support for all UART port index	2017-08-21 16:30:24 +00:00