4e9bb3308e
Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space. Some platforms have a different way of mapping the PCI config
space to memory. This patch renames the following configs to
make it clear that these configs are ECAM-specific:
- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH
Please refer to CB:57861 "Proposed coreboot Changes" for more
details.
BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
Make sure Jenkins verifies that builds on other boards
Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
129 lines
3.1 KiB
C
129 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/io.h>
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#include <bootblock_common.h>
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#include <build.h>
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#include <console/console.h>
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#include <device/pci_ops.h>
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#include <fsp/util.h>
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#include <pc80/mc146818rtc.h>
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#include <soc/gpio.h>
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#include <soc/iomap.h>
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#include <soc/iosf.h>
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#include <soc/lpc.h>
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#include <soc/msr.h>
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#include <soc/pm.h>
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#include <soc/spi.h>
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asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
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{
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/* Call lib/bootblock.c main */
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bootblock_main_with_basetime(base_timestamp);
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}
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static void program_base_addresses(void)
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{
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uint32_t reg;
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const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
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/* Memory Mapped IO registers. */
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reg = PMC_BASE_ADDRESS | 2;
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pci_write_config32(lpc_dev, PBASE, reg);
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reg = IO_BASE_ADDRESS | 2;
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pci_write_config32(lpc_dev, IOBASE, reg);
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reg = ILB_BASE_ADDRESS | 2;
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pci_write_config32(lpc_dev, IBASE, reg);
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reg = SPI_BASE_ADDRESS | 2;
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pci_write_config32(lpc_dev, SBASE, reg);
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reg = MPHY_BASE_ADDRESS | 2;
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pci_write_config32(lpc_dev, MPBASE, reg);
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reg = PUNIT_BASE_ADDRESS | 2;
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pci_write_config32(lpc_dev, PUBASE, reg);
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reg = RCBA_BASE_ADDRESS | 1;
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pci_write_config32(lpc_dev, RCBA, reg);
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/* IO Port Registers. */
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reg = ACPI_BASE_ADDRESS | 2;
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pci_write_config32(lpc_dev, ABASE, reg);
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reg = GPIO_BASE_ADDRESS | 2;
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pci_write_config32(lpc_dev, GBASE, reg);
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}
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static void tco_disable(void)
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{
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uint32_t reg;
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reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT);
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reg |= TCO_TMR_HALT;
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outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT);
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}
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static void spi_init(void)
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{
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void *scs = (void *)(SPI_BASE_ADDRESS + SCS);
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void *bcr = (void *)(SPI_BASE_ADDRESS + BCR);
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uint32_t reg;
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/* Disable generating SMI when setting WPD bit. */
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write32(scs, read32(scs) & ~SMIWPEN);
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/*
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* Enable caching and prefetching in the SPI controller. Disable
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* the SMM-only BIOS write and set WPD bit.
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*/
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reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD;
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reg &= ~EISS;
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write32(bcr, reg);
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}
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static void soc_rtc_init(void)
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{
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int rtc_failed = rtc_failure();
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if (rtc_failed) {
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printk(BIOS_ERR, "RTC Failure detected. Resetting date to %x/%x/%x%x\n",
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COREBOOT_BUILD_MONTH_BCD, COREBOOT_BUILD_DAY_BCD, 0x20,
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COREBOOT_BUILD_YEAR_BCD);
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}
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cmos_init(rtc_failed);
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}
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static void setup_mmconfig(void)
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{
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uint32_t reg;
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/*
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* Set up the MMCONF range. The register lives in the BUNIT. The IO variant of the
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* config access needs to be used initially to properly configure as the IOSF access
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* registers live in PCI config space.
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*/
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reg = 0;
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/* Clear the extended register. */
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pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg);
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reg = CONFIG_ECAM_MMCONF_BASE_ADDRESS | 1;
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pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg);
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reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) |
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IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN;
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pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg);
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}
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void bootblock_soc_early_init(void)
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{
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/* Allow memory-mapped PCI config access */
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setup_mmconfig();
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/* Early chipset initialization */
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program_base_addresses();
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tco_disable();
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}
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void bootblock_soc_init(void)
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{
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report_fsp_output();
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/* Continue chipset initialization */
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soc_rtc_init();
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set_max_freq();
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spi_init();
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lpc_init();
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}
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