Sridhar Siricilla b647e35119 soc/intel/alderlake: Add timestamp for cse_fw_sync ... The patch add timestamp around cse_fw_sync(). TEST=Verified on Brya, cbmem -t: 948:starting CSE firmware sync 1,381,577 (45,227) 949:finished CSE firmware sync 1,459,513 (77,936) Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Idba11417e0fc7c18d0d938a4293ec3aff1537fb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>		2021-12-23 14:42:28 +00:00
..
alderlake	soc/intel/alderlake: Add timestamp for cse_fw_sync	2021-12-23 14:42:28 +00:00
apollolake	Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"	2021-11-15 12:00:12 +00:00
baytrail	soc/intel/baytrail,denverton_ns: Call setup_lapic()	2021-12-15 12:10:02 +00:00
braswell	Rename ECAM-specific MMCONF Kconfigs	2021-11-10 17:24:16 +00:00
broadwell	Spell *Boot Guard* with a space for official spelling	2021-12-16 14:17:36 +00:00
cannonlake	soc/intel/cannonlake: Configure common FSP memory settings only once	2021-12-13 12:56:04 +00:00
common	soc/intel/common: Do not trigger crashlog on all resets by default	2021-12-20 17:49:53 +00:00
denverton_ns	soc/intel/denverton_ns: Use popcnt() helper	2021-12-17 21:41:39 +00:00
elkhartlake	soc/intel/elkhartlake: Hook up public microcode	2021-12-12 16:05:04 +00:00
icelake	soc/intel/common/thermal: Refactor thermal block to improve reusability	2021-11-25 07:18:04 +00:00
jasperlake	soc/intel/jasperlake: Hook up public microcode	2021-12-12 16:04:47 +00:00
quark	Rename ECAM-specific MMCONF Kconfigs	2021-11-10 17:24:16 +00:00
skylake	soc/intel/{skylake/cannonlake}: Fix bug in vr_config	2021-12-10 14:30:12 +00:00
tigerlake	soc/intel/common: Do not trigger crashlog on all resets by default	2021-12-20 17:49:53 +00:00
xeon_sp	commonlib/cbmem_id.h: Fix typo in macro name	2021-11-25 11:13:28 +00:00
Kconfig
Makefile.inc	soc/intel/common/cse: Add support for stitching CSE components	2021-10-19 16:09:08 +00:00