Shelley Chen 4e9bb3308e Rename ECAM-specific MMCONF Kconfigs ... Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>		2021-11-10 17:24:16 +00:00
..
acpi	Rename ECAM-specific MMCONF Kconfigs	2021-11-10 17:24:16 +00:00
bootblock	Rename ECAM-specific MMCONF Kconfigs	2021-11-10 17:24:16 +00:00
include/soc	soc/intel/braswell: Make num_cpus unsigned	2021-11-05 12:39:04 +00:00
romstage	soc/intel/braswell/romstage/romstage.c: Use __func__	2021-01-26 20:52:35 +00:00
acpi.c	soc/intel/braswell: Set GNVS DPTE via devicetree	2021-11-01 16:02:13 +00:00
chip.c	soc/intel/braswell: use mp_cpu_bus_init	2021-10-22 01:28:06 +00:00
chip.h	soc/intel/braswell: Set GNVS DPTE via devicetree	2021-11-01 16:02:13 +00:00
cpu.c	soc/intel/braswell: use mp_cpu_bus_init	2021-10-22 01:28:06 +00:00
elog.c	soc/intel: Remove unused <console/console.h>	2021-02-15 10:50:09 +00:00
emmc.c	soc/intel: Replace <soc/nvs.h> with <soc/device_nvs.h>	2021-01-03 11:35:51 +00:00
fadt.c	soc/intel: drop P_BLK support	2021-10-13 18:05:05 +00:00
gfx.c	{sb,soc}/intel/**/*.c: Use macros for PCI COMMAND bits	2020-07-26 21:17:50 +00:00
gpio.c	src/soc/intel: Drop unneeded empty lines	2020-09-21 16:15:25 +00:00
gpio_support.c
iosf.c	soc/intel/{baytrail,braswell}: Drop unneeded return	2020-07-25 10:19:14 +00:00
Kconfig	Rename ECAM-specific MMCONF Kconfigs	2021-11-10 17:24:16 +00:00
lpc_init.c	src/soc/intel: Drop unneeded empty lines	2020-09-21 16:15:25 +00:00
lpe.c	soc/intel: Replace bad uses of find_resource	2021-11-04 17:34:30 +00:00
lpss.c	soc/intel: Replace bad uses of find_resource	2021-11-04 17:34:30 +00:00
Makefile.inc	cpu/x86: Introduce and use CPU_X86_LAPIC	2021-10-26 17:44:14 +00:00
memmap.c	src: Update some incorrect config options in comments	2020-11-16 12:09:58 +00:00
northcluster.c	src/soc to src/superio: Fix spelling errors	2021-10-05 18:07:08 +00:00
pcie.c
placeholders.c
pmutil.c	soc/intel/braswell/pmutil.c: Define __SIMPLE_DEVICE__	2021-04-19 10:45:06 +00:00
ramstage.c	soc/intel/{baytrail,braswell,broadwell}: Remove unused <string.h>	2021-02-16 17:28:12 +00:00
sata.c	soc/intel: Remove unused <console/console.h>	2021-02-15 10:50:09 +00:00
scc.c	soc/intel: Replace bad uses of find_resource	2021-11-04 17:34:30 +00:00
sd.c	soc/intel: Replace <soc/nvs.h> with <soc/device_nvs.h>	2021-01-03 11:35:51 +00:00
smbus.c	soc/intel/braswell/smbus.c: Define __SIMPLE_DEVICE__	2021-04-19 10:44:40 +00:00
smihandler.c	sb,soc/intel: Remove no-op APMC for C-state and P-state	2021-01-25 10:37:13 +00:00
smm.c
southcluster.c	ACPI: Have single call-site for acpi_inject_nvsa()	2021-01-13 18:30:13 +00:00
tsc_freq.c	src: use ARRAY_SIZE where possible	2021-02-15 11:30:40 +00:00
xhci.c