4e9bb3308e
Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space. Some platforms have a different way of mapping the PCI config
space to memory. This patch renames the following configs to
make it clear that these configs are ECAM-specific:
- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH
Please refer to CB:57861 "Proposed coreboot Changes" for more
details.
BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
Make sure Jenkins verifies that builds on other boards
Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
120 lines
3.2 KiB
C
120 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file is created based on Intel Tiger Lake Processor SA Datasheet
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* Document number: 571131
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* Chapter number: 3
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <delay.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <intelblocks/power_limit.h>
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#include <intelblocks/systemagent.h>
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#include <soc/iomap.h>
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#include <soc/soc_chip.h>
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#include <soc/systemagent.h>
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/*
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* SoC implementation
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*
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* Add all known fixed memory ranges for Host Controller/Memory
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* controller.
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*/
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void soc_add_fixed_mmio_resources(struct device *dev, int *index)
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{
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static const struct sa_mmio_descriptor soc_fixed_resources[] = {
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{ PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
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"PCIEXBAR" },
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{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
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{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
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{ EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
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{ REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
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{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
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};
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sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
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ARRAY_SIZE(soc_fixed_resources));
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/* Add Vt-d resources if VT-d is enabled */
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if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
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return;
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sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
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ARRAY_SIZE(soc_vtd_resources));
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}
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/*
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* SoC implementation
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*
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* Perform System Agent Initialization during Ramstage phase.
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*/
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void soc_systemagent_init(struct device *dev)
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{
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struct soc_power_limits_config *soc_config;
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struct device *sa;
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uint16_t sa_pci_id;
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config_t *config;
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/* Get System Agent PCI ID */
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sa = pcidev_path_on_root(SA_DEVFN_ROOT);
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sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF;
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/* Enable Power Aware Interrupt Routing */
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enable_power_aware_intr();
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/* Enable BIOS Reset CPL */
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enable_bios_reset_cpl();
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/* Configure turbo power limits 1ms after reset complete bit */
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mdelay(1);
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config = config_of_soc();
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/*
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* Choose a power limits configuration based on the SoC SKU,
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* differentiated here based on SA PCI ID.
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*/
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switch (sa_pci_id) {
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case PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2:
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soc_config = &config->power_limits_config[POWER_LIMITS_U_2_CORE];
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break;
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case PCI_DEVICE_ID_INTEL_TGL_ID_U_4_2:
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soc_config = &config->power_limits_config[POWER_LIMITS_U_4_CORE];
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break;
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case PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2:
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soc_config = &config->power_limits_config[POWER_LIMITS_Y_2_CORE];
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break;
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case PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2:
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soc_config = &config->power_limits_config[POWER_LIMITS_Y_4_CORE];
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break;
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case PCI_DEVICE_ID_INTEL_TGL_ID_H_6_1:
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soc_config = &config->power_limits_config[POWER_LIMITS_H_6_CORE];
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break;
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case PCI_DEVICE_ID_INTEL_TGL_ID_H_8_1:
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soc_config = &config->power_limits_config[POWER_LIMITS_H_8_CORE];
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break;
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default:
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printk(BIOS_ERR, "TGL: unknown SA ID: 0x%4x, skipping power limits "
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"configuration\n", sa_pci_id);
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return;
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}
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set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
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}
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uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
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{
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switch (capid0_a_ddrsz) {
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case 1:
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return 8192;
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case 2:
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return 4096;
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case 3:
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return 2048;
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default:
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return 65536;
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}
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}
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