Lee Leahy b8f5323107 soc/intel/quark: Add the verstage files ... Add the files to support verstage for vboot. TEST=Build and run on Galileo Gen2 Change-Id: Icf87075012c08cf581c17d579e0763888c707265 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18040 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>		2017-03-13 21:25:27 +01:00
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apollolake	soc/intel/apollolake: Wrap lines at 80 columns	2017-03-13 17:52:40 +01:00
baytrail	google/rambi: add explicit pull-down for ram-id	2017-02-14 13:03:53 +01:00
braswell	intel: Fix copy/paste error in license text	2017-01-16 12:57:05 +01:00
broadwell	soc/intel/broadwell: Rework IGD's CDClk selection	2017-03-10 17:39:46 +01:00
common	soc/intel/common: Remove parenthesis	2017-03-13 17:09:02 +01:00
fsp_baytrail	fsp_baytrail: Enable graphic init per default	2017-01-13 17:42:26 +01:00
fsp_broadwell_de	intel: Fix copy/paste error in license text	2017-01-16 12:57:05 +01:00
quark	soc/intel/quark: Add the verstage files	2017-03-13 21:25:27 +01:00
sch	nb/intel/*/northbridge.c: Remove #include <device/hypertransport.h>	2017-01-06 18:15:03 +01:00
skylake	soc/intel/skylake:Add _DSM method to reduce D3 cold delay for eMMC controller	2017-03-10 11:19:04 +01:00