Matt DeVillier 474a7c51ce google/rambi: add explicit pull-down for ram-id ... Some variants need the internal pull resistor on GPIO_SSUS_40 set explicitly to pull down rather than disabling the pull, in order for the ram-id to be read correctly via GPIO. Correct this by adding a function to enable and set the internal pull and define its use as needed in the board's variant.h. Chromium source: branch: firmware-gnawty-5216.239.B /src/soc/intel/baytrail/baytrail/gpio.h#418 /src/mainboard/google/gnawty/romstage.c#60 Test: boot 4GB Candy board and observe correct RAM id, amount detected Change-Id: I8823c27385f4422184b5afa57f6048f7ff2a25ab Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18309 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>		2017-02-14 13:03:53 +01:00
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acpi
bootblock
include/soc	google/rambi: add explicit pull-down for ram-id	2017-02-14 13:03:53 +01:00
romstage	soc/intel/common: remove mrc cache assumptions	2016-12-15 07:51:35 +01:00
acpi.c
chip.c
chip.h
cpu.c
dptf.c
ehci.c
elog.c
emmc.c
gfx.c
gpio.c
hda.c
iosf.c
Kconfig	MMCONF_SUPPORT: Flip default to enabled	2016-12-07 13:00:31 +01:00
lpe.c
lpss.c
Makefile.inc
memmap.c
northcluster.c
pcie.c	src/soc: Add required space before opening parenthesis '('	2016-08-31 20:09:42 +02:00
perf_power.c
placeholders.c
pmutil.c
ramstage.c
refcode.c
reset.c
sata.c	src/soc: Add required space before opening parenthesis '('	2016-08-31 20:09:42 +02:00
scc.c
sd.c
smihandler.c	soc/intel/baytrail: use common Intel ACPI hardware definitions	2016-07-15 08:31:56 +02:00
smm.c
southcluster.c
spi.c	spi: Get rid of SPI_ATOMIC_SEQUENCING	2016-12-23 04:54:55 +01:00
stage_cache.c
tsc_freq.c
xhci.c