Furquan Shaikh b9b6f4d013 soc/intel: Drop unused lpss functions ... This change drops the following unused lpss functions and related code: * soc_lpss_controllers_list * is_dev_lpss These functions were added to determine if a controller is LPSS for performing IRQ configuration. But, these never got used and hence are being dropped. Change-Id: I27bdfbca7c199e823a0e4fdb277e3f22fb6bae7a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>		2021-06-07 11:35:08 +00:00
..
acpi	soc/intel/tigerlake: Return TBT PowerResource from PR0 and PR3	2021-05-27 14:40:09 +00:00
bootblock	soc/intel: Drop bootblock_cpu_init() function	2021-03-01 19:43:04 +00:00
include/soc	soc/intel/tigerlake: Add validity for TBT firmware authentication	2021-05-26 15:43:01 +00:00
romstage	soc/intel/alderlake: rename CONFIG_MAX_PCIE_CLOCKS to CONFIG_MAX_PCIE_CLOCK_SRC	2021-04-21 09:19:58 +00:00
spd	util: Add DDR4 generic SPD for H4AAG165WB-BCWE	2021-03-22 11:26:40 +00:00
acpi.c	soc/intel/tigerlake: Use device ID from pci_devs header file	2021-04-26 08:27:34 +00:00
chip.c	soc/intel: Replace open-coded buffer length calculation	2021-04-21 14:21:44 +00:00
chip.h	soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OC	2021-05-14 23:00:01 +00:00
chipset.cb	soc/intel/tigerlake: Remove obsolete CNVi Bluetooth PCI device	2021-03-15 06:27:15 +00:00
cpu.c	soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT	2021-05-07 06:05:37 +00:00
crashlog_lib.c	soc/intel/tigerlake: Re-use existing define in CrashLog implementation	2021-03-03 09:02:16 +00:00
dptf.c	dptf: Move platform-specific information to struct dptf_platform_info	2021-04-13 08:22:49 +00:00
elog.c	soc/intel/*: Update data types for variables holding PCH_DEVFN_* macros	2021-05-03 16:28:53 +00:00
espi.c	src: Match array format in function declarations and definitions	2021-05-13 18:34:38 +00:00
finalize.c	src: Include <arch/io.h> when appropriate	2020-10-26 06:44:40 +00:00
fsp_params.c	soc/intel: Drop unused lpss functions	2021-06-07 11:35:08 +00:00
gpio.c	soc/intel/tigerlake: Add known CPU Port IDs for GPIO communities	2021-05-06 04:12:41 +00:00
gspi.c
i2c.c
Kconfig	soc/intel/alderlake: rename CONFIG_MAX_PCIE_CLOCKS to CONFIG_MAX_PCIE_CLOCK_SRC	2021-04-21 09:19:58 +00:00
lockdown.c
Makefile.inc	cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y	2021-05-18 16:54:21 +00:00
me.c
meminit.c	soc/intel/tgl and tgl mb/google,intel: Use the newly added meminit block driver	2021-01-25 08:48:57 +00:00
p2sb.c
pmc.c	soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT	2021-05-07 06:05:37 +00:00
pmutil.c	soc/intel/*/pmutil.c: Align cosmetics across platforms	2021-02-24 11:34:42 +00:00
reset.c	soc/intel: Use of common reset code block	2020-11-02 10:43:53 +00:00
smihandler.c	soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster	2021-05-07 06:05:18 +00:00
soundwire.c
spi.c	src/soc/intel/tigerlake: Add SPI DMI Destination ID	2020-12-08 22:57:45 +00:00
systemagent.c	soc/intel: Replace SA_PCIEX_LENGTH Kconfig options	2021-01-30 23:14:08 +00:00
uart.c	soc/intel/*: drop UART pad configuration from common code	2021-03-12 08:48:03 +00:00
xhci.c	soc/intel/common: Adapt XHCI elog driver for reuse	2020-12-10 17:45:47 +00:00