coreboot-kgpe-d16/src
Dennis Wassenberg bd202bcdf3 nb/intel/sandybridge: Lock PAVPC
This makes CHIPSEC happy. We don't enable PAVP, but it shouldn't hurt
to lock it nevertheless.

Change-Id: I9428f0b6e8868832eb79f7aea24cbc7961c2aa8f
Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com>
Reviewed-on: https://review.coreboot.org/17352
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-08 01:35:42 +01:00
..
acpi src/acpi: Capitalize ACPI and SATA 2016-07-31 19:25:40 +02:00
arch PCI ops: MMCONF_SUPPORT_DEFAULT is required 2016-12-07 12:59:28 +01:00
commonlib lib: Add time stamp when starting to finalize chips 2016-12-07 20:14:25 +01:00
console Hook up libhwbase in ramstage 2016-11-29 23:45:40 +01:00
cpu MMCONF_SUPPORT: Flip default to enabled 2016-12-07 13:00:31 +01:00
device src/device: Get device structure by path type 2016-12-07 22:55:20 +01:00
drivers spi: Clean up SPI driver interface 2016-12-07 20:19:07 +01:00
ec sio/acpi: Add more magic bytes to ENTER/EXIT_CONFIG_MODE 2016-12-07 20:01:50 +01:00
include src/device: Get device structure by path type 2016-12-07 22:55:20 +01:00
lib lib: Add time stamp when starting to finalize chips 2016-12-07 20:14:25 +01:00
mainboard google/beltino: fix LED, simplify function for Tricky variant 2016-12-07 23:43:49 +01:00
northbridge nb/intel/sandybridge: Lock PAVPC 2016-12-08 01:35:42 +01:00
soc soc/broadwell: set EM4/EM5 registers based on cdclk 2016-12-07 23:54:14 +01:00
southbridge sb/intel/bd82x6x: Add TCO_Lock in finalize step 2016-12-08 01:35:22 +01:00
superio sio/ite/it8783ef: New super i/o chip 2016-12-07 20:02:17 +01:00
vboot commonlib/include: remove NEED_VB20_INTERNALS 2016-11-19 16:57:27 +01:00
vendorcode vendorcode/siemens: Ensure a given info block is available for a field 2016-12-06 09:59:11 +01:00
Kconfig PCI ops: MMCONF_SUPPORT_DEFAULT is required 2016-12-07 12:59:28 +01:00