ariel fang 88c5f90275 mb/google/brya/variants/primus: Update two GPIOs ... 1. Move M2_SSD_PLN_L to GPP_D3 for power loss notify function. 2. Set GPP_E21 as NC to remove LCLW_DET function BUG=b:190643562 Signed-off-by: Ariel Fang <ariel_fang@wistron.corp-partner.google.com> Change-Id: Id3c60adeb5d35c79a1c700937f93a80ad3587c5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56420 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-07-21 20:44:19 +00:00
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spd
variants	mb/google/brya/variants/primus: Update two GPIOs	2021-07-21 20:44:19 +00:00
board_info.txt
bootblock.c	mb/{google, intel}: Make use of `cpu/intel/cpu_ids.h'	2021-07-19 18:25:42 +00:00
chromeos.c	mb/google/brya: Finish support for ChromeOS GPIOs	2021-03-08 18:25:11 +00:00
chromeos.fmd	mb/google/brya: Reorganize flashmap	2021-03-09 18:45:00 +00:00
dsdt.asl	mb/google/brya: Enable WFC	2021-06-01 23:03:12 +00:00
ec.c
Kconfig	mb/google/brya: Create taeko variant	2021-07-21 16:24:04 +00:00
Kconfig.name	mb/google/brya: Create taeko variant	2021-07-21 16:24:04 +00:00
mainboard.asl	mb/google/brya: Implement SLP_S0_GATE signal	2021-03-18 22:31:36 +00:00
mainboard.c	mb/google/brya: Add variant specific soc chip config update	2021-07-21 16:22:59 +00:00
Makefile.inc
romstage.c	soc/intel/alderlake: Update mainboard_memory_init_params() argument	2021-06-24 07:55:12 +00:00
smihandler.c