1. Move M2_SSD_PLN_L to GPP_D3 for power loss notify function.
2. Set GPP_E21 as NC to remove LCLW_DET function
BUG=b:190643562
Signed-off-by: Ariel Fang <ariel_fang@wistron.corp-partner.google.com>
Change-Id: Id3c60adeb5d35c79a1c700937f93a80ad3587c5e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56420
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Program unused Cnvi BT UART GPIOs as NC since we are using
Bluetooth over USB mode for Brya.
Change-Id: I33a37ceb8a91603d2a193de5bdd1b6885eb3c319
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55317
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the taeko variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:193685558
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_TAEKO
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: If738849bc3103c52a4c4d8a8aaef3f90a62ad5c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56385
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add SPD support to gimble for LPDDR4 memory part MT53E1G32D2NP-046 WT:A and K4U6E3S4AA-MGCR.
BUG=b:191574298
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I4bfc18fd42c6ff2675e6f836c2ecc9617fac3aff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56329
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds support for variant specific soc chip config update
function.
Change-Id: Ic3a3ae0b409433e6dfa102c5e7a6322d4f78f730
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change adds mem_parts_uesd.txt that contains the new
memory parts used by primus and Makefile.inc generated by
gen_part_id.go using mem_parts_used.txt.
BUG=b:193813079
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I6aa37114f3a164a4f3c35dfc9b43e1106b825bff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
If two generic devices use the same number, device coming later
overrides the earlier device, as a result of this the static.c has
only one device.
In the case where we have UFC set to UFC_USB, this will result in
no IPU device scope in SSDT, since its entry will be set to disbled
after UFC probe.
TEST=Build, Boot and Check UFC camera preview with UFC=UFC_USB
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I034cb7da787313d1cb53484922149589ac0f1c5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
We need to reference correct USB port number for driver to
identify type-C port number correctly.
BUG=b:189476816
BRANCH=None
TEST=Check the transactions are happening on correct port. Also checked
retimer firmware update on both the ports.
Change-Id: I20c088ee81610155067abad086eba8d72f73ad60
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Create the kano variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:193052432
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_KANO
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib0670e346c113291054cb92fb57aae52f844e8c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56155
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the redrix variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:192052098
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_REDRIX
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I4cfa0bd84e1ba9f8140f95d18a6da960da8124ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch sets the disable the external voltage rails since brya
board doesn't have V1p05 and Vnn bypass rails implemented.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I1c4fdb38c5c56798935b2c6627a75c3f1ac9fbef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
brya0 is a reference and development platform, therefore it would be
helpful to have Crashlog enabled.
Change-Id: I936e73e808e0a05e8b7822cddbb5ee3fa7dee13e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
The brya EC supports S0ix hang detection, but it was not enabled in
coreboot as well, masking that event out of S0ix, therefore add it in to
the EC S0ix wake mask.
TEST=After EC prints "Warning: Detected sleep hang! Waking host up!",
the host actually wakes up
Change-Id: I2c699114abcd9a045a41858c731e4b6fe99d3000
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
P-sensor is swap by the latest schematic. Thus, swap the IRQ for correct
P-sensor.
BUG=b:192331122,b:181555900
TEST=check P-sensor driver can be probed without error.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3ccb31c1925e476e2ebb34b2439a491759472405
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This changes updates mainboard properties by adding DFP number and
power_gpio for each DFP.
Reference CB:55348
BUG=b:191897776
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I63c912980530e5c9f341bdbab18c07685fd77abf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
init overridetree.cb based on the schematic carbine_adl-p_proto_20210618_proto final.pdf
BUG=b:191213263
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I3f6875ef438b147436605629445d346a56896a87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
set GPP_C3 and GPP_C4 as NC since LAN function removal.
BUG=b:190643562
Change-Id: I21214d0a2904ba4347fbbbc74237aca6db22c345
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55933
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set GPP_B3 to APIC mode to avoid PCI IRQ conflict.
BUG=b:181555900
TEST=check dmesg there are no IRQ request errors like below.
genirq: Flags mismatch irq 27. 00002008 (sx932x_event) vs. 00000080 (idma64.1)
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idf88fae9e244858445c45e66e26715cebe0c93ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
1. Add 2 port 2 endpoint
2. Add support for OVTI5675
3. Guard entries in override device tree by FW_CONFIG
MIPI UFC is on I2C2
This configuration is as per P2 schematics
BUG=b:190674542
TEST=Build and Boot on Brya
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: Id3ef974994fd0d447e398b365cdf01d78c94cc4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
UFC on brya can be USB or MIPI
Add FW_CONFIG bit for this option
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I2f1492d7c769aba8da80763124dda474b32cfbfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This changes updates mainboard properties by adding DFP number and
power_gpio for each DFP.
Reference CB:54292
BUG=b:186521258
TEST=Updated BB retimer FW from 3.4 to 3.5 without any device
connected.
Change-Id: I24a02fd446cb66bda9e66e59802b4deea6894273
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This change adds mem_parts_uesd.txt that contains the only
memory parts used by primus for Proto build and Makefile.inc
generated by gen_part_id.go using mem_parts_used.txt.
BUG=b:186091208,b:189169995
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I423fd9ad4349c51c6e6b166734ae706509d6ac3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add Makefile.inc to include three generic LPDDR4 SPDs for the following
parts for Gimble:
DRAM Part Name DRAM ID to assign
MT53E512M32D2NP-046 WT:E 0 (0000)
H9HCNNNCPMMLXR-NEE 1 (0001)
H9HCNNNBKMMLXR-NEE 0 (0000)
BUG=b:191574298
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I60f95ac5ed7f3134882f6580335ec33632676796
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Set the GPIO configuration of gimble
BUG=b:191213263
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I667943578a2bf58cc5841564b8df5b6469d7594b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55717
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates mainboard_memory_init_params() function argument from
FSPM_UPD to FSP_M_CONFIG. Ideally mainboard_memory_init_params()
function don't need to override anything other than FSP_M_CONFIG UPDs
hence passing config block alone rather passing entire FSP-M UPD
structure.
Change-Id: I238870478a1427918abf888d71ba9c9fa80d3427
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Set the GPIO configuration of primus
BUG=b:190643562
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I405561ae8a44d95ffdc526241f9c52761f67ed35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change also restores GPIOs to their proper settings for prior board
revs.
BUG=b:189362981
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I89d7ba94dfbd5e4a000cdde7a0c65f38b53b722d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55325
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to meet timing requirement of WWAN reseting it in early GPIOs
and asserting Reset GPIO in ramstage
BUG=b:180166408
TEST=Build and boot Brya system and verify enumeration of L850 and FM350 devices
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: Id6d69696b6c645eec3fa314a608c69214bafba82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54912
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the gimble variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:190334274
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_GIMBLE
Change-Id: If425571d95b3b20910f890428fb5726ebad2fdf4
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55300
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch updates PMC Descriptor which is part of Descriptor Region if
system equipped with Alder lake A0 silicon. This change allows to use
unified Descriptor Region for Alder lake A0(CPU ID:0x906a0) and B0
(CPUD ID:0x906a1) silicons.
BUG=B:187431859
TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon if
not updated.
coreboot logs appear as below with this patch:
On First boot after flashing the image:
coreboot-coreboot-unknown.9999.4589c0f Wed Jun 9 18:23:43 UTC 2021 bootblock starting (log level: 8)...
CPU: Genuine Intel(R) 0000
CPU: ID 906a0, Alderlake Platform, ucode: 0000001a
..
FMAP: Found "FLASH" version 1.1 at 0x1804000.
FMAP: base = 0x0 size = 0x2000000 #areas = 32
FMAP: area SI_DESC found @ 0 (4096 bytes)
SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
Erasing flash addr 0 + 4 KiB
Update of PMC Descriptor successful, trigger GLOBAL RESET
Next boot after GLOBAL RESET:
coreboot-coreboot-unknown.9999.4589c0f Wed Jun 9 18:23:43 UTC 2021 bootblock starting (log level: 8)...
..
FMAP: area SI_DESC found @ 0 (4096 bytes)
SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
Update of PMC Descriptor is not required!
VBOOT: Loading verstage.
..
CBFS: Found 'fallback/verstage' @0x2264c0 size 0x16b08 in mcache @0xfef84d38
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I6d9a2ce0f0b3e386eefa1962ce706b58f31a8576
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Provide functions to allow for variants to override only a few pads from
the baseboard table.
BUG=b:189362981
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I3ae6c11ca8614d523f3402f1c1abb7c82124e473
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Power limits (PL1 and PL2) depend on the specific SKU of the CPU.
By expanding the SoC chip config power_limits_config member to
an array indexed by ADL_*_POWER_LIMITS_*_CORE macros, the
appropriate power limits are applied. Using this the correct
set of power limits are being selected from the array based on
system agent PCI ID. Based on this, chipset.cb file contains
the set of power limits being used by varieties of ADL boards.
These power limit values are as per document 619501.
BUG=None
BRANCH=None
TEST=Built and verified the following console output on below boards
On adlrvp (482):
CPU PL1 = 28 Watts
CPU PL2 = 64 Watts
On adlrvp (682):
CPU PL1 = 45 Watts
CPU PL2 = 115 Watts
On brya (282):
CPU PL1 = 15 Watts
CPU PL2 = 55 Watts
Change-Id: Ic1676e2b4d611cdc85e770f131d5b6d5ecd180be
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
This changes adds the EC_HOST_EVENT_USB_MUX to be dark resume source.
BUG=None
TEST=Build coreboot image successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I6f4dcbc60a6cb131f28de205bd9ef436f2b508eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55126
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I2C4 is not used pn Brya hence make below changes:
1. Disable it in SerialIoI2cMode.
2. Remove I2C4 config in common_soc_config.
TEST=Make sure FSP is not programming I2C4.
Change-Id: I94c72b7fac9d8a001913b5faa2c0c8a3e8b701e9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
For all of the audio devices in overridetree.cb add the probe matches
that will determine if the device should be enabled or not based on the
selected audio daughter board type.
AUDIO=MAX98357_ALC5682I_I2S: enable max98357, dmic1 and alc5682i
AUDIO=MAX98373_ALC5682_SNDW: enable max98373, dmic2 and alc5682
BUG=b:188696010
TEST=test different audio devices based on fw_config value:
> AUDIO=UNKNOWN
ectool cbi set 6 0x00000000 4 2
> AUDIO=MAX98357_ALC5682I_I2S
ectool cbi set 6 0x00000100 4 2
> AUDIO=MAX98373_ALC5682_SNDW
ectool cbi set 6 0x00000200 4 2
Change-Id: I6f159442516830f9d304d78c83f070e4fcff4a37
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The entries in the ACPI tables for the fingerprint module's SPI
configuration were incorrect.
1) The GPIO is routed to IOAPIC (and SCI), therefore in ACPI, it must be
described by Interrupt(), not GpioInt()
2) The chip-select signal was selected as 1, not 0 `device spi 0/1 on`
BUG=b:181635081
TEST=verified in kernel logs:
localhost # ~ dmesg|egrep 'cros-ec-dev|cros-ec-spi'
[ 4.569412] cros-ec-dev cros-ec-dev.1.auto: CrOS Fingerprint MCU detected
[ 4.575303] cros-ec-spi spi-PRP0001:00: Chrome EC device registered
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I9ef6c99f011969fc444e0c12b806529cb82bba3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55147
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the primus variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-generated by create_coreboot_variant.sh version 4.5.0)
BUG=b:188272162
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_PRIMUS
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I26787f296793b281b7f1ee1a7d240006163c6015
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
In order to support no MIPI camera variant, move related configuration into variant folder.
BUG=b:188272162
BRANCH=none
TEST=build no MIPI camera variant without error
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I4e64d078a8e39732ad29443c3b09ca008a7e902f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
1. Add 1 port and 1 endpoint
2. Add support for OVTI8856
WFC is on I2C0
BUG=None
BRANCH=None
TEST=Build and boot brya
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: Ic5e9c28f255bdf86a68ce80a4f853be4e7c7ccfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Enabling AC connect/disconnect wake events in brya to meet Chrome OS
wake requirements.
These changes are similar to Volteer and Shadowmountain.
BUG=none
BRANCH=None
TEST=manual tested DUT wakes for AC connect/disconnect in S0ix
Change-Id: I14b3efd429e3aa701af534f150baf35fcdeb9f35
Signed-off-by: madhusudanarao amara <madhusudanarao.amara@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54855
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 2f8a7046bb.
Reason for revert: CB:54752 makes this unnecessary
Change-Id: I3ad0bcafe50e3eafb9a106720c6c9ea5cb0efc4f
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54789
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
