Wonkyu Kim d250063c09 mb/intel/tglrvp: Enable SATA ... Enable both SATA ports for TGLRVP. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board with SATA memory Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I9f35682982a6c06522e58b0bbd7162ff02c37f32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38505 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-01-24 09:53:14 +00:00
..
acpi	src/acpi: Update license headers to SPDX	2020-01-02 14:49:00 +00:00
arch	arch/x86/post.c: Hide cmos_post_code from SMM context	2020-01-18 10:57:59 +00:00
commonlib	include/commonlib: Fix typos	2020-01-10 15:26:03 +00:00
console	console/post: NOPOST means NOPOST	2020-01-18 10:53:08 +00:00
cpu	cpu/intel/model_6?x{slot_1}: Leave enabling CONFIG_SMP to the mainboard	2020-01-18 22:07:47 +00:00
device	src/device: Update pci_class to PCI-SIG Specification	2020-01-10 10:55:49 +00:00
drivers	drivers/smmstore: Clarify Kconfig cbfs wording	2020-01-20 17:40:26 +00:00
ec	ec/google/chromeec: add support for fw_config cbi field	2020-01-22 15:43:42 +00:00
include	soc/intel/common: Add Elkhartlake Device IDs	2020-01-22 15:42:26 +00:00
lib	cbfs: Remove locator concept	2020-01-18 10:51:04 +00:00
mainboard	mb/intel/tglrvp: Enable SATA	2020-01-24 09:53:14 +00:00
northbridge	nb/intel/sandybridge: sort LANEBASE_* defines by their address	2020-01-16 08:40:10 +00:00
security	security/vboot: Allow UDC regardless of vboot state	2020-01-18 11:17:30 +00:00
soc	soc/intel/tigerlake: Enable SATA	2020-01-24 09:52:54 +00:00
southbridge	{soc,southbridge}/*/*/acpi: Add possibility to disable S4	2020-01-22 15:41:02 +00:00
superio	superio/nuvoton/nct5104d: Add virtual LDN for simple GPIO IO control	2020-01-20 11:09:57 +00:00
vendorcode	vc/amd/agesa: Fix out of bounds read	2020-01-13 11:22:40 +00:00
Kconfig	{soc,southbridge}/*/*/acpi: Add possibility to disable S4	2020-01-22 15:41:02 +00:00